I know this subject is very repetitive, but It's very confusing to me. I'm familiar to verilog coding and digital circuit designing but I haven't work with FPGAs. I want to learn it. could you please help me? Thanks.
Sure. Download Ise and get the webpack license - free, but you have to register and go through some hassle filling out a few forms.
I do all my work on smaller FPGAs and CPLDs, so the webpack license supports all the devices I need.
Really, there are only a few major parts of Ise you need to be concerned with. First, of course, is the HDL language of your choice. I also prefer VHDL, it may be a hair more verbose and requires you to specify many type conversions, but I think that latter bit is a plus!
Second, you need to learn how to run the simulator, and how to build test benches of stimuli for the VHDL logic to respond to. Not real hard, but REALLY gets verbose to flip bits on and off, delay a while, flip some more bits, etc.
The last parts are the constraints file and Impact to download the config to real hardware.
Xilinx' docs are not bad. If you can't find it there, they have forums that can give a lot of help.
Jon
thanks Jon. You helped me a lot.
Jon's post is pretty much spot on, I'd only add a slighly different perspective...
I see it differently : if you find yourself writing many type conversions, it usually shows a problem with the design. Something has been declared with the wrong type : step back, look at the design again.
When you see it, use the right type in the first place. Most of the conversions will disappear, leaving a cleaner, simpler design.
One of VHDL's strengths is the way the type system can help you, if you let it instead of fighting it.
But if you write the same flipping code more than twice, it's time to move it into a procedure.
Using VHDL at a higher level, it can become less verbose, more reusable, and certainly easier to understand.
Once you have grasped the basics, and move on to more complex projects, you'll want to look at advanced verification tools, such as OSVVM, and the VUnit testing framework.
Another strength of VHDL is that these tools are pure VHDL, free, and open-source, where alternatives might require you to move from Verilog to System Verilog and expensive closed source tools.
OSVVM:
VUnit
-- Brian
Thanks Brian, your comment is very helpful. after choosing the language, I should learn how to use FPGAs. could you please help me? I need your experience.
The tools have their own peculiarities. I am no longer familiar with the Xilinx tools. The parts all the tools have in common is that you have to specify your pin out with attention to the location of special purpose signals like clocks or differential I/Os. You will also need to set up timing constraints to help placement and routing to meet your needs for speed.
If you have a design that will be hard to meet timing, you may need to specify placement of critical components. That is very unique to each brand of tool.
-- Rick
I started learning on my own after I bought an Altera dev board. They have great documentation and video tutorials and their software is fairly intuitive. After you create an account go to their documentation section and take a look.
Would recommend this board for the price and available resources (it's 30$ on Arrow). It has some tutorials to get you started:
The single best moment while learning was when I managed to get VGA output to my monitor. It required some soldering though - there are more expensive boards that have the plug already connected:
Yeah, not bad. I recently got one of these...
Haven't done much with it yet, still learning the tools. They have an Android app to test the Bluetooth but I don't have anything Android. Durn.
-- Rick
'Making a simple, structured and efficient VHDL testbench - Step-by-step' is a powerpoint presentation and free webinar that shows novices how to get started making good testbenches, *and* experienced designers how to properly structure your testbenches. The example DUT is a very simple interrupt controller, and the testbench itself uses the free and open source Bitvis Utility Library (compatible with VHDL 93, 2002 and 2008).
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