FPGA decoupling calculation

Hi Kim, I've not got much time so here's a few pointers:-

IMO, Xilinx publish excessive requirements which covers their arse if anything should go wrong. Fair enough. However, you should know that it's fairly difficult to get this wrong, indeed, some folks (not me!) on this newsgroup apparently use very few bypass caps.

Free capacitor parameter stuff.:-

Above a few 10's of MHz, all same sized caps have the same impedance. (See murata thing above) Just use 0402 1uF for everything. One per pin is more than enough. Make sure your board has a ground plane, try to use two vias for each cap terminal.

Here's some stuff on where to place your caps.

Or, ignore that stuff, sooo 20th C. Better bypass here:-

Finally, there are caps hidden in the FPGAs themselves. Go to your university's chemistry dept. and ask for some HF to find them!

Also, STFW ! ;-)

HTH, Syms.

If you route the Xilinx recommended number of CAPs, you either have no room for signal breakout or the bypass caps end up far away from the FPGA. The calculation also seems to forget about the interinsic C and L of the supply layers.

My rule is: - try to implement a good ground plain, no swiss cheese - try to place one 0603/0402 cap in X5/7R near each supply pin with the traces to the FPGA as short as possible

Hi Uwe, Indeed. I notice their own dev. boards don't follow the XAPP recomendation. Hmmm. Cheers, Syms.

The headers in your post suggest you are using Windows. That's good, because you can download LTSpice and use that.

Like all simulations, the results are only as good as your models. In particular, you'll end up with lumped approximations which may result in resonances that don't appear on the real board. (The real board will have distributed capacitance, and also dielectric loss (which gets rid of a lot of the impedance peaks).)

Regards, Allan

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yea i noticed that too, the Spartan3E starter board dosent follow the XAPP recommendation

A spreadsheet can give a rough estimate as well...more later

Look up the specs on the caps for the parasitic L and R. Now you can build a spreadsheet that calculates the complex impedance Z as a function of frequency of each cap type (i.e. 10uF, 4.7uF, etc.). Knowing that, you can now compute the impedance of your PDS as a function of frequency as well. Then graph it and you'll see your expected impedance profile. You'll also want to factor in your PCB impedance as well, but start with the caps.

I'm not sure where you're getting the 20dB/decade assumption since the drop would depend entirely on the characteristics of the functions being generated. If you could build a really good pseudo random generator set of outputs from the FPGA, then one would expect a roughly flat frequency response across the entire frequency band. Most real designs though are not terribly random and would have some rolloff but trying to take advantage of that in designing the power delivery for an unknown FPGA design might not be the best approach.

By the way, going about figuring out the number and values of caps to use based on current demand and voltage ripple over a frequency range as you're doing is exactly the right approach. Don't forget about the PCB stackup though, closely spaced power/ground plane pairs supply the low impedance path that you'll need to connect up the caps (which are the source of charge for the load) with the load itself. This PCB impedance can be factored into that same spreadsheet model.

Kevin Jennings

Using LTSpice with wine on linux many times :-)

"Symon" wrote

I don't know what you mean by very few but, for the 1.2V VCCINT, I used 12 caps in my last big FPGA board ;-)

For a Stratix II 180 1.2V decoupling, I have:

I'm pretty happy with that stuff. I have a glitch less than 30mV when the FPGA current goes from 2A to 25A in a few µs.

I also put small coax connectors to be able to monitor the power rails at least for the prototypes:

I use that too.

IMHO the LLM21 are better ;-)

Marc

Hi Marc,

Anyway, if you get a spare moment, I'd appreciate you opinion of:-

Cheers, Syms.

Hi Allan, I second that. I thought I'd mention that there's also a Yahoo group for LTSpice users.

The L depends strongly on how you connect the cap to the power/ground planes. How many vias are you using? Where are they placed? What is the via diameter? Is there a trace from the cap pad to the via? ...

What we'd do is make sure each voltage has a pretty hunky copper pour that's separated from the ground plane by a thin dielectric layer. Then bypass each pour to ground with maybe four to six 0.33 uF, 0603 ceramic caps.

That's it.

John

well, im looking for a more theoretic answer for determing the decoupling capacitors ... if i switch 2A with a risetime of 0.5ns how can i determine the current vs frequency or the impedance vs frequency for the harmonics of 50Mhz switching frequency ... the impedance requirement cant be constant over the complete frequency spectrum

"Symon" wrote

I was surprised too and I had to redesign my power supply. :( It's a Stratix II 180 full at 86% and running at 200MHz.

They compared to an 8 pins IDC connector which has an ESL of 100pH. The LLM21 has a 45pH ESL. The 2 added pins make a big difference as they are placed on the short sides of the caps.

Some people even prefer 0402s to X2Y:

For decoupling the other supply rails, I used one 2.2µF 0402 per pin + 2 x

There are also other low ESL caps like the LGA and LICA:

Marc

Hi Kim,

There lies the problem. You're not going to get a proper answer without considering the physical layout of the system. As Hal says, the layout and attachment of the caps is as important as their own characteristics. Also, remember that you're trying to bypass the IC die, not the pads for the BGA on the PCB. So, the BGA package and its balls must be part of the calculation, indeed it can have a significant effect. IC manufacturers embed bypass caps in the package for good reason. All this must be taken into account.

You should consider the design loaded into the FPGA. If you can reduce the number of simultaneously switching circuits, the PDS requirement is easier to meet.

The only way I know of to get an accurate answer to your question is to model the whole lot in a 3-D field solver like HFSS. As you're a student (I guess) maybe Ansoft will lend you a seat? You also need to talk to your FPGA vendor to get models of their package. If you do this, we'd all be grateful to see the results!

John's solution is a good one; I would maybe consider substituting the X2Y parts for his 0603 parts. Try googling puddle site:x2y.com to read how a copper 'puddle', like John's pours, can 'pool' vias.

Lastly, these days the capacitors are often cheaper than the cost to attach them. Fewer more expensive parts can be a cost saver.

HTH., Syms.

Hi Marc, Many thanks, that's very interesting. I misread the Murata datasheet and got the LLMs mixed up with LLLs. (I must stop posting late after returning from the pub!) The AVX parts are neat too. That gives me plenty to think about. Much appreciated, Syms.

Did you click 'Thread Next'? Ouch! Syms.

Why?

John

The Fourier transform of the (current) waveform will give you the current vs. frequency spectrum. The actual problem comes with the capacitor itself which, including its leads, will turn inductive as the frequency increases.

-- glen