FPGA Configuration

First make sure you have a stable 6.3V AC heater supply (50Hz or 60Hz is fine). The configuration bit stream is modulated onto this using QPSK

You don't need HT during configuration, but a negative grid bias will keep down leakage currents.

It depends on how lazy they seem to be. Where someone clearly has made no significant effort to discover simple information for themselves, why should we make a serious reply? My experience is that those whose first resort is to ask someone else will continue to do it until discouraged. I'd guess they are the people whose parents peeled apples for them.

Since you work for a vendor, perhaps it's your job continually to spoon-feed those who find it tiresome to open a book, to spend a few seconds on Google or, in this case, to download the manufacturer's data sheet. The rest of us don't have time for lazy people. There are enough serious problems to be addressed.

Hi Mike, As it happens, this came up at the weekend in a discussion with some old friends I hadn't seen for a while. I agree with you that it's a good idea to configure the FPGA with a valves. (Tubes in the US). The bits are warmer and more rounded. (This latter property is useful in fixed point DSP implementations). Although transistor fed bits are cleaner, the valve fed bits have more air. It is absolutely vital that, whether using solid state or vapour state programming, the configuration traces on the PCB are made of oxygen free copper. Otherwise, the bits get too much air. I expect. HTH., Syms.

p.s.

I can understand the differences in air, but as much as the marketers and "electrophyles" talk about it, I just can't tell any difference in bit roundness.

KJ

The more round the bits, the better they take the corners...

Andy

Atti you should be more precise in aswer 1:

bye Thomas

Hi Thomas

you could have been more precise with the spelling too :)

I was wondering when somebody makes this remark, you are right 1) is YES/NO YES

• Xilinx all except S3AN

• Altera all except MAX2 (I think its more a FPGA than CPLD)

• Lattice all except XP,XP2,machXO,ispFPGA

NO

• Actel all

• Quicklogic all

• Altera MAX2

• Lattice XP,XP2,machXO,ispFPGA

• Xilinx S3AN

A N T T I