FPGA config sizes

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We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?  

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.

--  

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement  

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Re: FPGA config sizes
Am 08.11.19 um 20:08 schrieb John Larkin:
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The size of the programming file is in the data sheet. It is constant
and does not depend on the implemented circuitry.

Newer FPGAs may allow to program only some sectors of the chip.

regards, Gerhard

Re: FPGA config sizes
On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
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Anyone know what a "PHB type question" is?  

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  Rick C.

  - Get 1,000 miles of free Supercharging
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Re: FPGA config sizes
On 2019-11-08 Rick C wrote in comp.arch.fpga:
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https://dilbert.com/search_results?terms=phb

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Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

Corry's Law:
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Re: FPGA config sizes
On Friday, November 8, 2019 at 5:48:04 PM UTC-5, Stef wrote:
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Yeah, someone explained in the other group.  A bit obscure, methinks.  

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  Rick C.

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Re: FPGA config sizes
On 09/11/2019 00:12, Rick C wrote:
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Nah.  I get suspicious of any engineer who doesn't know the term PHB!

It's like not understanding the term SEP.


Re: FPGA config sizes
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I had to think a bit to come up with PHB, but I got it.  I've no idea
what SEP is.

But then I'm acronymn dumb (and too lazy to try and google it right
now.)

(I've got a feeling a "whoosh" at my expense is incoming...)

--Mark





Re: FPGA config sizes
On 11/11/2019 17:33, gtwrek wrote:
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"Somebody else's problem".  It's a term from Douglas Adams:

"""
An SEP is something we can't see, or don't see, or our brain doesn't let  
us see, because we think that it's somebody else's problem. That?s what  
SEP means. Somebody Else?s Problem. The brain just edits it out, it's  
like a blind spot.
"""

<https://en.wikipedia.org/wiki/Somebody_else 's_problem>


It is very useful in all kinds of engineering, for helping focus on the  
task /you/ have to do instead of everyone else's tasks.

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You need to swat up on your TLA's :-)


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Re: FPGA config sizes
On 11/11/2019 18:10, David Brown wrote:
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"swot" up, rather - and I need to work on my spelling!


Re: FPGA config sizes
On 08/11/2019 19:08, John Larkin wrote:
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The uncompressed FPGA configuration file size does not change with the  
device utilization.
You need to look at the data sheet for the particular device.
Obviously the compressed file size will be variable - with anything from  
0% to near 100% compression ratio dependent on content and compression  
algorithm.

Re: FPGA config sizes
On Friday, November 8, 2019 at 1:09:04 PM UTC-6, John Larkin wrote:
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There's a general trend of about 60-80 bits per LUT input (can go higher).
4LUT has ~4-6 inputs, 6LUT or ALM 6-8 inputs.  Count the number of LUTs in the part and multiply.  Some go as high as 400M+ configuration bits.

Jim Brakefield

Re: FPGA config sizes
On 08/11/2019 19:08, John Larkin wrote:
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 From Lattice ECP5 sysCONFIG Usage Guide FPGA-TN-02039.

LFE5-45 - 8.86Mb


 From Xilinx UG470
Xilinx Artix 35T and 50T need the same 17.536 Mb

MK

Re: FPGA config sizes
On 09/11/2019 09:49, Michael Kellett wrote:
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Why complicate things with memory soooo cheap ??? Just store raw data...

Re: FPGA config sizes
wrote:

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Compression could save bootup time. The Artix7 that I'm using now is
only 17 mbits, but some of the Vertix chips are approaching a gigabit.
Luckily, I can't afford them.

https://www.digikey.com/product-detail/en/xilinx-inc/XCVU37P-3FSVH2892E/122-XCVU37P-3FSVH2892E-ND/10445719

Probably lots of config bits.





--  

John Larkin         Highland Technology, Inc

lunatic fringe electronics  


Re: FPGA config sizes


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My PHB answer would be 32 Mbit.

However, "mid-range" FPGA is a very broad definition. These days I would
call mid-range something like the Spartan 7 family, but probably someone
could argue that it is already low-range. So you could choose 32 Mbit
(which is the maximum bitstream size required for the Spartan-7 and for a
mid-range Artix 7) or go a little further to accomodate also the mid-range
Kintex-7. See table 1-1:

https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

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Fletto i muscoli e sono nel vuoto.

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