FPGA clock frequency

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Hai,


I am pretty clear about cutoff and  sampling frequency of FIR filter.

Wat r all the FIR filter constraints to be considered to set FPGA
clock frequency before targetting to FPGA device?

I guess i should consider maximum number of taps and maximum sampling
frequency used by the FIR filter...am i correct?

can i implement a FIR filter of 256-taps(all the taps clocked
synchronously),1Ghz cutoff frequency,2.5GS/s with a input FPGA clock
frequency of 250Mhz?

pls clarify this.

regards,
faza


Re: FPGA clock frequency

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Can you spell "surface acoustic wave"?

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So you plan to clock your FPGA at 1/10th the filter's
sampling frequency.  That means you must process ten
samples on each clock cycle.  Do you know how to do that?

Since you plan for a cutoff frequency of 1GHz, you can't
undersample the filter's output.  So you not only need
to process ten input samples on every clock, but also
you must generate ten output samples on every clock.
That would lead to "interesting" I/O requirements.
There will also be "interesting" internal resource
requirements, unless your filter coefficients are
very sparse.

Were the figures you gave us (Fclk25%0MHz, Fs=2.5GHz,
Fc=1GHz) intended to reflect a real problem? Or were
they simply random numbers?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Re: FPGA clock frequency
Can you spell "surface acoustic wave"?
That was the maximum cutoff frequency support i am expecting to
get ....as my FIR filter is generic it should support from low to high
frequency

That means you must process ten samples on each clock cycle. A0%Do you
know how to do that?
my design accepts 1 sample/clockcycle

but also you must generate ten output samples on every clock.
current design takes number of taps specified+2 clock cycles to
generate o/p for each sample.can u pls suggest for the current design
wat should be the Fclk i should set to achieve 256 taps and 1GS/s,Is
it possible?.And how u relate Fclk with Fs and Fc?as those Fs and Fc
are constraints to generate coefficients why we have to consider in
hardware implementation?How to decide Fclk?since the maximum clock
rate depends on the logic and routing delay of the design...

Were the figures you gave us (Fclk3D%250MHz, Fs3D%2.5GHz,
 Fc3D%1GHz) intended to reflect a real problem? Or were
 they simply random numbers?
Those r the worst case i should support..

regards,
faz



wrote:
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Re: FPGA clock frequency

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I believe the only way it to try it.  There are tradeoffs
between throughput and logic that can only be done trying
different designs.  Especially as routing delay is likely
very important.

The exact number of pipeline stages depends on routing
delay, logic levels, etc.

-- glen


Re: FPGA clock frequency

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Hi Jonathan,
Ha, that reminds me of a DSP course some of us attended in the mid-eighties.
The lecturer chap tried to convince us that DSP was the only way to make
linear phase filters. Sadly for him, several of us knew how our colour
tellys extracted the chrominace signal!
Cheers, Syms.



Re: FPGA clock frequency

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Putting to one side for the moment the universal hazards of
appearing in public - undone fly-zips, remains of yesterday's
supper on the tie, iridescent facial pustules, and the like -
there are two obvious ways a trainer or lecturer can make
a complete idiot of themselves:
(1) simply getting something completely wrong - hard to
    avoid in a training course of several days' duration,
    human frailty being what it is;
(2) assuming that the audience/students/clients know
    less than the trainer does.

These days, my preferred response to (2) is simply to enjoy
the fact that whenever I deliver a class I learn a bunch
of interesting stuff from the students.  I hope they don't
mind too much, given that they're paying :-)  In any case,
a certain humility is in order; most of us know quite a
lot about some things, but embarrassingly little about
other things.  I reckon it'll be time to give up when I
find myself no longer willing to learn from students.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
We've slightly trimmed the long signature. Click to see the full one.
Re: FPGA clock frequency
Hai jonathan,

U have not given comments for my questions...

regards,
faza

wrote:
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Re: FPGA clock frequency

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That's because you have me completely baffled.

You tell us you need 2.5G samples/sec but you have a
250MHz clock frequency.  I responded by pointing out
that this implies ten samples per clock, which is
something that seems to me to be completely obvious.  
You responded that you have one sample per clock.

Consider this example:  Someone says to me that
they want advice on how to build a staircase.
In particular, they want the staircase to
rise by 30 metres, and to have exactly 15 steps.
I point out that this would require each step
to be 2 metres high, and the response comes
back "Each step is to be 20cm high".
How do I respond intelligently to that?

I think I am entitled to my confusion.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
We've slightly trimmed the long signature. Click to see the full one.
Re: FPGA clock frequency
Just forget about that example...pls tell how sampling frequency
decides the Fclk in wat factor they are related and why?

say for simple case:

fc3D%5khz
fs3D%8khz
taps3D%16
fclk3D%? (considering my current design)

pls clarify..

regards,
faz







wrote:
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Re: FPGA clock frequency

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sheesh... just *think about it* for five minutes...

PROBLEM STATEMENT
~~~~~~~~~~~~~~~~~~

Every time the FPGA's clock ticks, it can do something.

Once per sample, you get a new input data item for your
filter and you need to spit out a new result from the
output of your filter.  It isn't as easy as this if you
are doing interpolation or decimation, but let's not
worry about that extra complication right now.

So...

POSSIBLE OUTCOMES
~~~~~~~~~~~~~~~~~

If you can deal with one input data item on each
clock tick - the obvious, simple, common case - then
you need to run the clock at exactly Fsample.

If you can deal with N input data items on each
clock tick, then you can run the clock at Fsample/N.
In practice that's likely to be quite difficult,
but it is definitely possible if you have some way to
gather up N input samples and deliver them to the
FPGA in a single hit.

If you choose to do the processing a little bit at
a time, and as a result you need M clock ticks to
deal with each data sample, then you need to run the
clock at M x Fsample.  This might allow you to get
away with fewer multipliers than filter taps, or
perhaps use bit-serial arithmetic, or some other
resource-saving tricks.  Obviously, if Fsample
is rather slow (as it would be for audio) and
Fclk can be much higher, then this is likely to
be the right way to proceed - use fewer multipliers,
and do each filter sample over several clock cycles.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

What parts of that are difficult, or non-obvious?

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Oh, and by the way...

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You can't build a low-pass filter with 5kHz cutoff
and 8kHz sampling frequency, thanks to a little
theorem from a bloke called Nyquist.

This doesn't Bode well, does it? :-)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Re: FPGA clock frequency

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Ah.  Thanks for your relatively novel suggestion [sorry]
which I had overlooked...
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
We've slightly trimmed the long signature. Click to see the full one.
Re: FPGA clock frequency
Hai,

Jonathan:simple, common case - then
you need to run the clock at exactly Fsample.

Faza:Still iam unable to trace how Fs will decide Fclk :

consider the following experiment i carried out in simulation level:

I generated the filter coefficients with the following parameters
using MATLAB FDA tool:
fc3D%3khz
fs3D%8khz
N3D%8
type3D%LP filter
design method3D%constra. least square

The generated 8 filter coefficients before hand is given as an input
to my design and it performs convolution operation with 8 impulse
samples .To get all the 8 coefficients come out
properly the following condition should be satisfied:
number of input samples 3D% number of coefficients.

Number of clock cylces to process each coefficient 3D% number of taps
+23D%10
so to process all the 8 coefficients with 8 impulse it is taking
10*83D%80 clock cycles

I got the same number of clock cycle(80 clock cycles) count for the
following:
fc3D%3khz
fs3D%12khz(different sampling frequency)
N3D%8
type3D%LP filter
design method3D%constra. least square

I guess u understood my design now...


so in the design  number of clock cycles are decided only with number
of taps not with sampling frequency as suggested by u since i am not
using xilinx core generator..

My questions to u:

pls explain...So for the above example wat is the fclk value ?(fs3D%8khz
and fs3D%12kHz with N3D%8)

In general for N3D%256 ,
My design will take (256+2) *2563D%66048 clock cycles

wat is the Fclk value with N3D%256?which xilinx device i can select for
implementation?

In general convolution process:
number of o/p samples3D%number of input sample + number of coeffie -1

But in my design
number of o/p sample 3D%number of input sample3D%number of coeffie
I have to append zero to my input samples so that it should be equal
to the filter coefficients to get all the coefficients otherwise i
will miss the o/p sample..
Is the above correct?pls clarify..

Thanks in advance

regards,
faza



wrote:
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Re: FPGA clock frequency

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Hi Faza,
I'll have a go.
Design your filter with Fs = 1 .
Let's say you designed it with a cutoff frequency of Fc where Fc < Fs/2 .
If you then clock this filter with a frequency of kFs, the cut off frequency
will be kFc .
Mmmm, hotwings.

HTH., Syms.



Re: FPGA clock frequency

    You must understand the difference between sample frequency (Fs) and FP=
GA  =

clock frequency...

    If your FPGA clock frequency is the same as your Fs then it's simple.
    If your FPGA clock frequency is higher (say, N times higher) than your =
Fs  =

then, the multiplier and adders could make N operations per sample (but =
 =

still only one operation per FPGA clock)
    If your FPGA clock frequency is lower than your Fs then you will need t=
o  =

use a parallel implementation since you have more samples than the FPGA =
 =

can deal with...

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    Well you decide the clock frequency... it should be equal or greater th=
an  =

Fs, for instance you can process your 12k signal with a 12k clock or a 1=
2  =

MHz clock...

    Also on these filters it's latency that is of interest, not the total  =

number of clocks to process a signal, since generally you operate on  =

continuous signals which have no known length (the data just comes...)  =

unless the signal is something like a video frame where you do have a  =

fixed amount of data...

Re: FPGA clock frequency
If you then clock this filter with a frequency of kFs, the cut off
frequency
will be kFc .

so u mean to say eventhough i generate the filter coefficients before
hand using FDA tool,i should set the Fclk by considering  the sampling
frequency and cutoff frequency for which i have generated the filter
coefficients..am i correct??

     If your FPGA clock frequency is the same as your Fs then it's
simple.
        If your FPGA clock frequency is higher (say, N times higher)
than your Fs
then, the multiplier and adders could make N operations per sample
(but
still only one operation per FPGA clock)
        If your FPGA clock frequency is lower than your Fs then you
will need to
use a parallel implementation since you have more samples than the
FPGA
can deal with.....

In that case how it is possible to fix fclk  which can support a
maximum sampling frequency till 600Mhz?

regards,
faza




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Re: FPGA clock frequency

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    Sorry, I mixed up the words ;) here's the correct one...

    You have a clock frequency Fclock.
    And a sample frequency Fsample.

    Suppose your impulse response length is N taps.

    If Fclock 3D% N * Fsample this is simple.

    Every N periods of Fclock it receives a sample.
    Then, N times, it takes a coefficient, and multiplies it with the  =

appropriate sample of the input :

    sum of Coeff(n) * Input(T-n) for n in [0,1 ... N-1]

    So it takes N clocks to process a sample because you use 1 multiplier a=
nd  =

you have N taps.

    Now if you use N multipliers you can process everything in one clock an=
d  =

therefore use Fclock 3D% Fsample. But you are going to use much more sli=
ces  =

in your FPGA.

    And if you have Fclock 3D% N * X * Fsample

    Then your filter is faster than what you need, but that is not a proble=
m,  =

once an input sample is processed, it will just sit idle waiting for the=
  =

next input sample.
    In this case you could process X channels instead of 1 channel still  =

using 1 multiplier, by using the time the silicon is idle to process the=
  =

other channels.

    Get it ?

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    Not necessarily ;)

    An impulse response is just a list of numbers. It does not have a cutof=
f  =

frequency. If it is a filter all it can have is a cutoff frequency ratio=
  =

which is a number without a Unit (no hertz, just a number), for instance=
 r  =

3D% 0.1 for a lowpass filter.
    Only when you say "the sample rate is Fs" then you can say "the cutoff =
of  =

this impulse response when used on a signal of frequency Fs is r * Fs" o=
r  =

0.1 Fs in this case.

    If you change the Fs it will just scale.

    Now if your processing is not done in real time, say for instance you  =

sample a chunk of data at Fs then you store the data in a buffer then yo=
u  =

stop sampling and you take the time to filter it, you can use any clock =
 =

you want since it's not in real time anymore.

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    No, you should set the clock frequency so that it's practical for you.

    Say your Fsample is 1 MHz
    you have N 3D% 10 taps in your filter
    for each sample you need 10 multiplications and 10 additions
    it takes a clock cycle to do a multiply + accumulate

    So you need a Fsample * N 3D% 10 MHz clock at least.

    But if you have other stuff in the FPGA running at 50 MHz you can use 5=
0  =

MHz instead.
    The filter will just sleep during 40 clock cycles then work for 10 cycl=
es  =

then sleep again etc.

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    Well I have bad news for you lol.
    Since the multipliers in your FPGA don't reach that frequency you will =
 =

need to use several multipliers and adders in parallel.
    For instance if you have 10 taps and 600 MHz you need 6 billion MACs/s =
 =

and if your multipliers run at 100 MHz (for example) each provides 100  =

million MAC/s so you're going to need 60 multipliers and a spaghetti  =

monster of logic.

    And since the FPGA fabric doesn't run at 600 MHz (unless you're rich)  =

you'll need to input several samples in parallel and add still more  =

spaghetti logic to coordinate all this stuff.

    What is the signal you want to filter ?
    Who chose the sample frequency ?
    Is it a REAL application which NEEDS that speed IN REAL TIME ? If it is=
,  =

it is going to be very EXPENSIVE.
    What is it that you want to do ?






Re: FPGA clock frequency

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    Well with N input samples and M taps you get N+M-1 output samples but i=
f  =

you are streaming a real time signal, noone cares about the boundary  =

conditions, so you can say that roughly number of input samples 3D% numb=
er  =

of output samples

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    Yes you have to zero pad. If you stop the input stream, your filter wil=
l  =

go to sleep waiting for more data which doesn't come, so the output will=
  =

be truncated.

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    OK then if it's audio why do you mention crazy sample rates like 600 MH=
z ?
    For audio ultimate quality is 192 kHz which is easy to do in FPGA.

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    Then choose a realistic input frequency...

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    Suppose you have 8 channels of 192 kHz audio in real time that's  =

1.536.000 samples/s, now if you use 256 taps that's about 400 million  =

MAC/s which means you can do it with a $10 FPGA.


Re: FPGA clock frequency
 I am planning to support 256-taps with direct
 form FIR filter which suffers from less speed and more hardware
 resources compared to distributed arithmetic architecture( i dont
know
 about this)

I have tested my design with inputs as  impulse test,step
test,sine,square,sawtooth,pulse and white noise...I dont know how to
check for overflow?wat is the test case?

regards,
faza


PFC wrote:
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Re: FPGA clock frequency
 I am planning to support 256-taps with direct
 form FIR filter which suffers from less speed and more hardware
 resources compared to distributed arithmetic architecture( i dont
know
 about this)

I have tested my design with inputs as  impulse test,step
test,sine,square,sawtooth,pulse and white noise...I dont know how to
check for overflow?wat is the test case?

regards,
faza

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Re: FPGA clock frequency
I am planning to support 256-taps with direct
 form FIR filter ...
======
The question really was to your motivations and design goals. Possible
answers might be:

"I read somewhere that I could."
"I want to build an 8-channel, 16-band graphic equalizer for my home
theater."
"To make a brick wall filter for my sub-woofer."
"To disguise my voice when I call co-workers in the middle of the night."
"I love karaoke."

In any case, the background and specifics fill multiple chapters in
textbooks. I don't expect anyone can condense it down into a digestible
newsgroup message for you. The best you'll get is a reading list. Google is
your friend there.

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I have tested my design with inputs as  impulse test,step
test,sine,square,sawtooth,pulse and white noise...I dont know how to
check for overflow?wat is the test case?

======
Quantization effects is a whole chapter in itself.



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