FPGA clock frequency

Hai,

I am pretty clear about cutoff and sampling frequency of FIR filter.

Wat r all the FIR filter constraints to be considered to set FPGA clock frequency before targetting to FPGA device?

I guess i should consider maximum number of taps and maximum sampling frequency used by the FIR filter...am i correct?

can i implement a FIR filter of 256-taps(all the taps clocked synchronously),1Ghz cutoff frequency,2.5GS/s with a input FPGA clock frequency of 250Mhz?

pls clarify this.

regards, faza

Reply to
fazulu deen
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Can you spell "surface acoustic wave"?

So you plan to clock your FPGA at 1/10th the filter's sampling frequency. That means you must process ten samples on each clock cycle. Do you know how to do that?

Since you plan for a cutoff frequency of 1GHz, you can't undersample the filter's output. So you not only need to process ten input samples on every clock, but also you must generate ten output samples on every clock. That would lead to "interesting" I/O requirements. There will also be "interesting" internal resource requirements, unless your filter coefficients are very sparse.

Were the figures you gave us (Fclk=250MHz, Fs=2.5GHz, Fc=1GHz) intended to reflect a real problem? Or were they simply random numbers?

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Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

Can you spell "surface acoustic wave"? That was the maximum cutoff frequency support i am expecting to get ....as my FIR filter is generic it should support from low to high frequency

That means you must process ten samples on each clock cycle. =A0Do you know how to do that? my design accepts 1 sample/clockcycle

but also you must generate ten output samples on every clock. current design takes number of taps specified+2 clock cycles to generate o/p for each sample.can u pls suggest for the current design wat should be the Fclk i should set to achieve 256 taps and 1GS/s,Is it possible?.And how u relate Fclk with Fs and Fc?as those Fs and Fc are constraints to generate coefficients why we have to consider in hardware implementation?How to decide Fclk?since the maximum clock rate depends on the logic and routing delay of the design...

Were the figures you gave us (Fclk=3D250MHz, Fs=3D2.5GHz, Fc=3D1GHz) intended to reflect a real problem? Or were they simply random numbers? Those r the worst case i should support..

regards, faz

Reply to
faza

Hi Jonathan, Ha, that reminds me of a DSP course some of us attended in the mid-eighties. The lecturer chap tried to convince us that DSP was the only way to make linear phase filters. Sadly for him, several of us knew how our colour tellys extracted the chrominace signal! Cheers, Syms.

Reply to
Symon

Putting to one side for the moment the universal hazards of appearing in public - undone fly-zips, remains of yesterday's supper on the tie, iridescent facial pustules, and the like - there are two obvious ways a trainer or lecturer can make a complete idiot of themselves: (1) simply getting something completely wrong - hard to avoid in a training course of several days' duration, human frailty being what it is; (2) assuming that the audience/students/clients know less than the trainer does.

These days, my preferred response to (2) is simply to enjoy the fact that whenever I deliver a class I learn a bunch of interesting stuff from the students. I hope they don't mind too much, given that they're paying :-) In any case, a certain humility is in order; most of us know quite a lot about some things, but embarrassingly little about other things. I reckon it'll be time to give up when I find myself no longer willing to learn from students.

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Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

Hai jonathan,

U have not given comments for my questions...

regards, faza

es.

Reply to
faza

That's because you have me completely baffled.

You tell us you need 2.5G samples/sec but you have a

250MHz clock frequency. I responded by pointing out that this implies ten samples per clock, which is something that seems to me to be completely obvious. You responded that you have one sample per clock.

Consider this example: Someone says to me that they want advice on how to build a staircase. In particular, they want the staircase to rise by 30 metres, and to have exactly 15 steps. I point out that this would require each step to be 2 metres high, and the response comes back "Each step is to be 20cm high". How do I respond intelligently to that?

I think I am entitled to my confusion.

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Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

Just forget about that example...pls tell how sampling frequency decides the Fclk in wat factor they are related and why?

say for simple case:

fc=3D5khz fs=3D8khz taps=3D16 fclk=3D? (considering my current design)

pls clarify..

regards, faz

Reply to
faza

sheesh... just *think about it* for five minutes...

PROBLEM STATEMENT ~~~~~~~~~~~~~~~~~~

Every time the FPGA's clock ticks, it can do something.

Once per sample, you get a new input data item for your filter and you need to spit out a new result from the output of your filter. It isn't as easy as this if you are doing interpolation or decimation, but let's not worry about that extra complication right now.

So...

POSSIBLE OUTCOMES ~~~~~~~~~~~~~~~~~

If you can deal with one input data item on each clock tick - the obvious, simple, common case - then you need to run the clock at exactly Fsample.

If you can deal with N input data items on each clock tick, then you can run the clock at Fsample/N. In practice that's likely to be quite difficult, but it is definitely possible if you have some way to gather up N input samples and deliver them to the FPGA in a single hit.

If you choose to do the processing a little bit at a time, and as a result you need M clock ticks to deal with each data sample, then you need to run the clock at M x Fsample. This might allow you to get away with fewer multipliers than filter taps, or perhaps use bit-serial arithmetic, or some other resource-saving tricks. Obviously, if Fsample is rather slow (as it would be for audio) and Fclk can be much higher, then this is likely to be the right way to proceed - use fewer multipliers, and do each filter sample over several clock cycles.

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

What parts of that are difficult, or non-obvious?

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Oh, and by the way...

You can't build a low-pass filter with 5kHz cutoff and 8kHz sampling frequency, thanks to a little theorem from a bloke called Nyquist.

This doesn't Bode well, does it? :-)

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Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

It appears you *aren't* "pretty clear about cutoff and sampling frequency." From your discussion so far, it seems that you don't know (and therefor respect) the breadth of filter requirements from audio, through video, to RF systems and the myriad of other applications in between.

You appear to want to design a digital filter that is all things to all people. It can't be done. No one design will satisfy all needs.

It further seems that you don't know the fundamentals of signal processing to understand what a "Nyquist frequency" is or how it affects what you're trying to accomplish. It's like someone who doesn't know how to multiply wanting to take up calculus.

As an electrical engineer with knowledge on how to wash clothes, I would never try to design a clothes washer that should accomodate single users in mobile homes to industrial-sized operations like hotels. First, I'm not an appliance designer though I know how to cut metal and drill holes. Second, I have the foresight to understand that I *cannot* provide a solution that will meet the demands of such a broad spectrum of designers.

I'd suggest you simply abandon your quest since it appears that you have no direction available to you except for 1)your knowledge that there is such a thing as an "FIR filter" and 2) the professionals, students, and hobbyists that frequent this newsgroup.

If you had an idea of the scope and knew the underlying fundamentals, I'd encourage you. You are starting from SO FAR off from where you need to be that I'd encourage taking up a very different pursuit. Perhaps a summer of reading up on signal processing?

Good luck in wherever life takes you,

- John_H

Reply to
John_H

I hesitate to say anything here. I agree with all you said, except in tone, with which I can't disagree more. And while I cherish intellectual curiosity, I also am in no position to even toy with volunteering to be an online mentor. So, ...

Addressed elsewhere in this NG today, I believe. Good luck, Faza.

Reply to
MikeWhy

Sorry for the non-digestive mistake made by me... as fs>=2fm and 0 news: snipped-for-privacy@k13g2000hse.googlegroups.com...

Reply to
faza

Ah. Thanks for your relatively novel suggestion [sorry] which I had overlooked...

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Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

Hai,

Jonathan:simple, common case - then you need to run the clock at exactly Fsample.

Faza:Still iam unable to trace how Fs will decide Fclk :

consider the following experiment i carried out in simulation level:

I generated the filter coefficients with the following parameters using MATLAB FDA tool: fc=3D3khz fs=3D8khz N=3D8 type=3DLP filter design method=3Dconstra. least square

The generated 8 filter coefficients before hand is given as an input to my design and it performs convolution operation with 8 impulse samples{1,0,0,0,0,0,0,0} .To get all the 8 coefficients come out properly the following condition should be satisfied: number of input samples =3D number of coefficients.

Number of clock cylces to process each coefficient =3D number of taps

+2=3D10 so to process all the 8 coefficients with 8 impulse it is taking 10*8=3D80 clock cycles

I got the same number of clock cycle(80 clock cycles) count for the following: fc=3D3khz fs=3D12khz(different sampling frequency) N=3D8 type=3DLP filter design method=3Dconstra. least square

I guess u understood my design now...

so in the design number of clock cycles are decided only with number of taps not with sampling frequency as suggested by u since i am not using xilinx core generator..

My questions to u:

pls explain...So for the above example wat is the fclk value ?(fs=3D8khz and fs=3D12kHz with N=3D8)

In general for N=3D256 , My design will take (256+2) *256=3D66048 clock cycles

wat is the Fclk value with N=3D256?which xilinx device i can select for implementation?

In general convolution process: number of o/p samples=3Dnumber of input sample + number of coeffie -1

But in my design number of o/p sample =3Dnumber of input sample=3Dnumber of coeffie I have to append zero to my input samples so that it should be equal to the filter coefficients to get all the coefficients otherwise i will miss the o/p sample.. Is the above correct?pls clarify..

Thanks in advance

regards, faza

Reply to
faza

Hi Faza, I'll have a go. Design your filter with Fs = 1 . Let's say you designed it with a cutoff frequency of Fc where Fc < Fs/2 . If you then clock this filter with a frequency of kFs, the cut off frequency will be kFc . Mmmm, hotwings.

HTH., Syms.

Reply to
Symon

You must understand the difference between sample frequency (Fs) and FP= GA =

clock frequency...

If your FPGA clock frequency is the same as your Fs then it's simple. If your FPGA clock frequency is higher (say, N times higher) than your = Fs =

then, the multiplier and adders could make N operations per sample (but = =

still only one operation per FPGA clock) If your FPGA clock frequency is lower than your Fs then you will need t= o =

use a parallel implementation since you have more samples than the FPGA = =

can deal with...

khz =

Well you decide the clock frequency... it should be equal or greater th= an =

Fs, for instance you can process your 12k signal with a 12k clock or a 1=

2 =

MHz clock...

Also on these filters it's latency that is of interest, not the total =

number of clocks to process a signal, since generally you operate on =

continuous signals which have no known length (the data just comes...) =

unless the signal is something like a video frame where you do have a =

fixed amount of data...

Reply to
PFC

If you then clock this filter with a frequency of kFs, the cut off frequency will be kFc .

so u mean to say eventhough i generate the filter coefficients before hand using FDA tool,i should set the Fclk by considering the sampling frequency and cutoff frequency for which i have generated the filter coefficients..am i correct??

If your FPGA clock frequency is the same as your Fs then it's simple. If your FPGA clock frequency is higher (say, N times higher) than your Fs then, the multiplier and adders could make N operations per sample (but still only one operation per FPGA clock) If your FPGA clock frequency is lower than your Fs then you will need to use a parallel implementation since you have more samples than the FPGA can deal with.....

In that case how it is possible to fix fclk which can support a maximum sampling frequency till 600Mhz?

regards, faza

y (Fs) and FPGA =A0

t's simple.

r) than your Fs =A0

=A0

u will need to =A0

=A0

=3D8khz =A0

or greater than =A0

=A0

t the total =A0

Reply to
faza

I believe the only way it to try it. There are tradeoffs between throughput and logic that can only be done trying different designs. Especially as routing delay is likely very important.

The exact number of pipeline stages depends on routing delay, logic levels, etc.

-- glen

Reply to
glen herrmannsfeldt

Suppose your task is to generate the sum of 8 numbers rather than something as complex as an FIR.

How many clock cycles will it take to add these 8 numbers?

The answer can be one.

FPGAs can perform operations in parallel during any one clock. These FPGAs are not serial processors.

The way to design a high sample-rate, 8-operand adder would be to pipeline the operations. You have to read up on what pipelining means in digital design.

This is - again - an absolutely fundamental concept that you haven't grasped before taking on a design.

You have no chance of processing data at 600 MHz even if the FPGA is capable of 600 MHz operation because you do not understand the fundamentals of hardware design, ,uch less the nuances.

I suggest once again - stop your pursuit. As an alternative, PLEASE pursue some local help from educators or professionals that can help take you by the hand and START you down the path of hardware design.

You are trying to accomplish something WAY beyond your capabilities and you are NOT doing your homework with respect to your needs.

Matlab is fun to play with but it gives you no sense of what it takes to truly implement a design.

Apologies to you and others for the tone - again - but you are not understanding that you have NO CHANCE of reaching your goals because you are not willing to pursue the fundamental research on your own to be ABLE to start a design with extreme goals.

I would encourage people who work hard to get the fundamental understanding needed to pursue these kinds of designs. You are not one of those people.

- John_H

Reply to
John_H

Hai ,

U have not answered my following question..

so u mean to say eventhough i generate the filter coefficients before hand using FDA tool,i should set the Fclk by considering the sampling frequency and cutoff frequency for which i have generated the filter coefficients..am i correct??

regards, faza

John_H wrote:

Reply to
faza

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