I need to connect the Xilinx ML402 board to the 3.3V CMOS chip. I am concerned about the ESD that could burn the CMOS chip.
I am concerned about the possibility of the ESD when CMOS is being connected or disconnected from the FPGA board's header, even though I would do it when both devices are turned off. I know that this depends on the chip itself, but I wonder if there are any general precautions that I could follow that would make this steps less hazardous? Is it more safe to set all the FPGA board's outputs to high impedance state once the task has been done before turning the board off?
The complete loop:
- FPGA creates control signals, including clock, that are sent through the board's header to the 3.3V CMOS chip.
- CMOS chip generates some data on its outputs that are connected to the FPGA board's header.
Thanks,
-Dan