FPGA board connected to CMOS chip: ESD hazards?

I need to connect the Xilinx ML402 board to the 3.3V CMOS chip. I am concerned about the ESD that could burn the CMOS chip.

I am concerned about the possibility of the ESD when CMOS is being connected or disconnected from the FPGA board's header, even though I would do it when both devices are turned off. I know that this depends on the chip itself, but I wonder if there are any general precautions that I could follow that would make this steps less hazardous? Is it more safe to set all the FPGA board's outputs to high impedance state once the task has been done before turning the board off?

The complete loop:

- FPGA creates control signals, including clock, that are sent through the board's header to the 3.3V CMOS chip.

- CMOS chip generates some data on its outputs that are connected to the FPGA board's header.

Thanks,

-Dan

Reply to
EEngineer
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After a quick look at the chematic the maximum supply voltage is

3.3v@3A. It would be worth checking what the maximum unloaded/no load voltage is. That will give a maximum possible voltage that this CMOS device will see if powered up.

You should be putting the device in or out with the PCB powered down. You may want to discharge any supply decoupling capacitors with some cable. You are using a grounded wrist strap.

Andy

Reply to
Andy Botterill

Dan,

Connecting, and disconnecting cables, or headers, of parts mounted on boards is not usually an ESD issue.

ESD is thousands of volts, from static electricity accumulation (usually on your person). Usually holding each assembly in your hands is enough to insure the potential difference between them is small (your skin and body neutralizes any charge difference between the two while you hold them). This does mean that you use both hands, so the two assemblies are neutral to each other.

Sounds like you are concerned about "hot plugging" or connecting and disconnecting live (or will be live soon) interfaces.

So, which is it? Damage from very high static voltages? Or damage from voltages within the normal operating range of the device when inserted live into a system?

As far as Xilinx FPGAs go, we publish our human body model ESD and machine model ESD specifications, and we also have no problem with live insertion (power on), as long as ground connects first, before an IO connects.

The reason why we suggest that grounds mate first, is that the ground provides the return path for any transients, and the self-protecting IO structures are better at protecting themselves if they share a ground.

Aust> I need to connect the Xilinx ML402 board to the 3.3V CMOS chip. I am

Reply to
austin

Good that FPGA ML402 board with Virtex 4 is safe, but how about this boards influence onto CMOS prototype chip - I am more concerned about it because CMOS chip cost is 20x higher then the FPGA board! It is

3.3V TSMC .35um technology.
Reply to
EEngineer

Disconnecting won't be a problem. When you connect the boards together, do as Austin says and make sure the grounds connect first. Alternatively, wear a earthing strap, or just touch a nearby PC case, and connect the grounds together with your sweaty fingers. (This is why electronic engineers always shake hands before exchanging boards! Of course, if you're swapping boards with an atractive engineer (yeah, right!!) french kissing provides a better contact.) HTH., Syms. xx

Reply to
Symon

EEngineer,

-snip-

If this is a custom chip manufactured by TSMC, I have no idea how sensitive it is to ESD or any other electrical stress. That would depend on how the IC designers chose to do their ESD protection, and how they protected their output from damage when shorted to ground or Vcc.

The ML402 board outputs are connected to the Virtex 4 chip, so depending on how you have the Vcco banks powered and how the device is configured, these IOs will either be; ground, logic high, or tristate. If the ML402 is not powered, all IOs look like a diode from the IP pin to Vcco, and a diode from ground to the IO pin. AT power ON, before configuration, all IOs are tristate.

If the external CMOS IC is powered, and the ML402 is not, then the external IC sees the diodes to Vcco of the Virtex 4 bank (if they are outputs).

Since you suggest to power both down, connect, and power both up, I don't see any issues with that.

If you touch both the ML402 and the external CMOS chip, then their potential is equal, and no zap will occur when they connect to each other.

Make sure that you work on an ESD conducting work surface, and wear a wrist strap connected to that surface (so you, the parts, the boards, the bench, are all at the same potential.

If the IC designers did their job properly, and used TSMNC's foundry ESD protection cells, then you should have no worries at all.

But, you should always use the ESD mat, and wrist strap anyway (just good practice).

Austin

Reply to
austin

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