FPGA behaviour when its used resource is >90% ?

Hi, We are using Xilinx Spartan2E in our platform and so far functioning of every logical cores was looking good. Today, I saw some weird behaviour after addng additional logic, all of sudden I was missing some signals coming out of FPGA and some signals looks different. This additional logic does not interfer with the exisitng logic cores. I am reaching upper limit of FPGA resource but still I can fit in all the logic cores.

So my question is, by utilizing the FPGA resource around 90%, does the behaviour of FPGA logics becomes unpredictible ?

Any pointers or suggestions in this regard is much appreciated.

Thank you in advance.

-Kiran

Reply to
kkumar
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Is the timing analysis still good ?

Rgds Andr=E9

Reply to
ALuPin

schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...

the logic utilization numer is somewhat magic/bogus, but reaching the limit makes the probability of unexplained behaviour larger, yes.

at the very basics a rock solid design should work. should work no matter what, if it runs the toolflow it should work (no matter the utilization). but its hardly ever so in real life. so adding unrelated logic (even when total utilization is not nearly at the max) may introduce unexpected failures.

there is no direct advice for you, lots of troubleshooting may be required. the extra logic may iterfere to the way the rest of the logic can be placed what makes the timing different and that can cause problems that did happen before

Antti

Reply to
Antti Lukats

Look at possible timing constraints violation. If neccessary, make constraints stricter, by increasing the frequency and/or adding jitter to the clocks

Reply to
Zara

Kiran, please send me some design files that you can share, and I'll take a look

Aurash

snipped-for-privacy@northernpower.com wrote:

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Reply to
Aurelian Lazarut

The addition of the new logic may have caused increased routing delays.

Reply to
Mike Harrison

Hi Antii

How can i identify the unrelated logic ? what is the meaning of unrelated logic. ?

could you please explain about it ?

regards bijoy

Reply to
bijoy

If your design is _properly_ constrained, and if the timing analysis after a build says everything's OK, then the amount of logic in the device shouldn't have any effect on the performance.

Nial.

------------------------------------------------------------- Nial Stewart Developments Ltd FPGA and High Speed Digital Design

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Reply to
Nial Stewart

unrelated logic means just what it says .. unrelated.. that means logic which doesn't have an interconnect. It might even be from different parts of the design. The only thing they have in common is they have nothing to do with each other. A bit like reality TV but without the camera :-)

Simon

logic. ?

Reply to
Simon Peacock

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