Hi, We are using Xilinx Spartan2E in our platform and so far functioning of every logical cores was looking good. Today, I saw some weird behaviour after addng additional logic, all of sudden I was missing some signals coming out of FPGA and some signals looks different. This additional logic does not interfer with the exisitng logic cores. I am reaching upper limit of FPGA resource but still I can fit in all the logic cores.
So my question is, by utilizing the FPGA resource around 90%, does the behaviour of FPGA logics becomes unpredictible ?
Any pointers or suggestions in this regard is much appreciated.
Thank you in advance.
-Kiran