hi
I need help with my async desgin. I'm using xilinx virtex-ii. I'm very new with async stuff and so my understanding is very limited-- particularly different fpga architechures. (and async terminology.)
Here is what I want to do:
module async(clk,loopbackclk,....) input clk; output loobackclk; reg loopbackclk; // decl , init and reset stuff omitted always @(clk) begin case (state) case 0: begin // do stuff state
You are not likely to succeed without doing hand place and route because of the delays in the FPGA. You need to be very careful to eliminate hazards due to race conditions in your design using proper cover terms. Also, remember that the logic is implemented conceptually as small look-up tables, so you need to be careful about any glitches generated while traversing the LUT. Also, be aware that 'wires' in an FPGA add delay, so routing can become very important in order to avoid adding unintended delays. Yes, it can be done, but the existing tools are not meant for asynchronous design (and will quickly get you into trouble if you depend blindly on them), and the FPGAs are optimized for synchronous design. Generally speaking, you'll probably be using local signals for clock in this case, so the global clock buffers are likely to be of little or no interest to you (I think that is what you are asking).
--
--Ray Andraka, P.E.
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