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FPGA as "Differential SSTL_2" clock driver

Hi.. Is it recommended to use following scheme, to generate "Differential SSTL_2" clock signals which are sourcing DDR SDRAM & another controller.

  1. Normal 125 MHz LVTTL clock source(Oscillator) feeding clock to FPGA.
  2. FPGA functionality inverts this clock.
  3. The same i/p clock & inverted clock are sent out of FPGA, with setting I/O standard of these to outputs as "OBUF_SSTL2_I".

If this scheme is ok, will there be any constrain on using particular family of FPGA like Spartan 2, Spartan 3 or virtex etc.

Cheers, Manish

Reply to
Manish
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Manish,

It is better to use the DDR FF in the IOB to do clock forwarding with the least duty cycle distortion. One IOB gets the DDR FF with the D tied to Vcc for the top FF,and the D tied to GND on the bottom FF, and the other (complement) IOB has the top D tied to GND, and the bottom D tied to Vcc.

Aust> Hi..

Reply to
Austin Lesea

Hello Austin, thanks a lot for this scheme. This is far better than the schemes I tried. (Taking DCM "0 degree" & "180 degree" shifted clocks, normal inversion & passing through SSTL OBufs.) I have two more queries in this regard,

  1. As a Spartan3 primitive - "FDDRRSE" is being used, this solution restricts the use of SP3 device (& V2, V2Pro) is there any way-out if one needs to use SP2, Virtex devices ?
2.In my design I need one more LVTTL 125 MHz clock out-of FPGA which should be phase-alligned with these SSTL clocks. The Post-PNR simulation that i have carried-out reveals that there is a phase differance between crossing-edges of SSTL pair & this LVTTL clock, of the order of 857 ps.is there any compensation technique fo this as well. (I have tried using I/Os whose physical locations are close to each other)

Manish

Reply to
Manish

Manish,

See below,

Aust> Hello Austin,

Nope. Have to go back to using two separate BUFG clocks, CLK0 and CLK180.

There is always a slight (unavoidable) difference when you change IO standards. You clould use another DLL(DCM) to phase shift that output if that 857 ps is a problem.

Reply to
Austin Lesea

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