Hello ALL,
I have a design with two global clocks. I have data I need to transfer from one clock domain to another. I am aware of existence of FIFO blocks :), but it seems to be too expensive to spend a block-ram and other resources for every boundary crossing. To avoid using FIFO blocks we created a handshake schematic, based on some triggers and small FSM. This solution is proven to work in hardware error-free for almost 40 hours. First domain clock frequency is 25MHz or 125MHz (depending on mode); second domain clock frequency is 166MHz.
Naturally, some triggers in out design are metastable. Is it possible to get some intermediate voltage level at the output of trigger in FPGA if input signal on its Data input violates setup or hold times? In my design I assume I don't get any intermediate level voltages at the trigger outputs. What about signal I input into FPGA from outside? Is it possible to get some intermediate voltage levels on the trigger outputs by violating setup-hold times and/or IO standard voltage levels?
With best regards, Vladimir S. Mirgorodsky