FPGA Advantage and Xilinx Specific Libs (like Unisim)

What's the best way to get the Xilinx libs like Unisim working for simulating a design in FPGA Advantage 6.1? I got it working before, but I have no idea what I did last time, and I need to set it up again.

Also, if I just comment out the library-related statements, should it synthesize properly in Precision? And is it possible to synthesize IP from the Xilinx EDK in anything but XST?

Thanks, Mike

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Mike Delaney
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