four phase clock using DCM with xilinx FPGA

Multiple DCM's? Phase shift capabilities of DCM's? ChipSync?

To name a few....

What's 312 MHz for?

Hi motty,

I need four equally-spaced sample phases to sample input data so that jitter will not cause any problem. The input data rate is 312MHz. So I need clk0, clk90, clk180 and clk270 with 312MHz working frequency. The DCM can be used to generate these four phase clocks, but it can't support such high frequency in Virtex 4. With Phase shift capabilities of DCM's, ChipSync, I am not familiar to them. Can you explain it more detail? thanks.

"motty =D0=B4=B5=C0=A3=BA "

Is your 312 MHz clock input to the FPGA or is it derived internally using a DCM clocked from some other input clock? Is the data phase-related to the clock? If it is realted to the 312 clock, then how BAD is the jitter? How closed will the data eye be?

The DCM's feature a finite phase shifting capability. I can't remember the frequency limits associated with using it, but that info can be found in the Virtex4 documentation. There would likely be issues with aligning the clocks from different DCM's.

If you really need 4 phases at that speed it may be better using the IDELAY's that are available on the FPGA I/O's. You'd have to input as many data streams as you need phases for though. Instead of using multiple clocks, you'd use multiple time-offset data streams.

Each option has its technical problems and challenges associated with it. Again, all the information on the technolgy can be found in the Virtex4 documentation, applications notes, etc.

well, the 312MHz clock is a input to FPGA. I do need four phases to sample the data so that data jitter could be reduce. It is very interesting that DCM could not output clk90 and clk270 when set it to high speed mode -- i got this information from Xilinx FAE and simulated this with ModelSim, but their datasheet and user guide doesn't mention this. My design has based on these four pahse clock and DCM performance and my PCB is ready for this. I have to find a way to solve this.

by the way, what do you mean by that "IDELAY"? thanks.

"motty =D0=B4=B5=C0=A3=BA "

The DCM's limitations are explained in the Virtex 4 Switching Characteristics data sheet which is found on their website. I've found that you have to dig deeper on all technology to find real world behavior. The User Guide is not the definitive answer. It really only glosses over all the available features -- which are a lot! More detail is found in other documentation and application notes. I would never build a PCB based on just the user guide. Sorry.

The Virtex 4 development boards are a VERY good investment. You can try out all the features and figure out what you need.

You can read about IDELAY is the User Guide to begin with. Then you'd have to investigate the Switching Characteristics of IDELAY. And their is also a ChipSync User Guide that REALLY goes in to detail about the IDELAY.

thanks

"motty =D0=B4=B5=C0=A3=BA "

The V4 can generate clk_90 and clk_270 from the DCM in high speed mode. Your FAE was wrong - only previous generation devices had this limitation. To see this is simulation use the DCM_BASE or DCM_ADV primitive instead of DCM.