Hi all,
When do Formal Equivalent Check (RTL and Gate Level) , I remember that the tool compare the comb logic between D-FF .
But when synthesis use re-timing and gated clock, can LEC tool compare RTL and Gate?
And is gated clock one form of re-timing?
I am reading a paper from SNUG about gated clock (How to successfully use gated clock...) but I cannot understand the waveform...
Best regards, Davy