Which is interesting, because that offers a lot more than Xilinx's subset testing - and as Paul also mentions, it is the Prototyping, and tool flows, that make a large difference in taking this step.
What is pretty much the same, in X & A's 'custom' offerings, is both will do the component testing, on their FPGA testers.
Unlike other ASIC vendors, the FPGA players have (very) large investments in the SW side of their business. Of course HardCopy paths are only for a tiny % of customers, so from a design-start viewpoint, they are insiginifcant, but the revenue potential of that small group are significant.
Still, if I were a Xilinx stock holder I might be a bit worried about their ignoring this sector. Let's see where they stand in 2008..
Let's see, Xilinx is "ignoring" a piece of a 155 M$ business with lousy margins and 9 other vendors competing and willing to drop prices below their costs?
As a Xilinx stockholder, I am pleased to see that Xilinx can keep their eye on the prize, and not stray off to the "gold ring du jour."
I do agree that having a cost reduction path is important for business.
I do not agree that spending a proportion of your revenue is warranted to "capture" it. A simple ROI calculation will reveal if it is real business, or just plain dumb.
Toshiba figured it out.
LSI figured it out.
We figured it out years ago.
Two others figured it out (too late as they drove themselves right into the ground).
I know it's a mistake getting involved in this thread, but...
here are some observations on EasyPath and (Structured) ASICs which don't appear to have come up elsewhere:
1 - EasyPath has an NRE. I don't have real numbers, but Xilinx's literature gives figures between $75K and $300K, and an MOQ of 50K pieces. It's not cheap.
2 - If you commit to EasyPath, you can't change your design without paying the NRE again. In this respect, EasyPath is the same as an ASIC. You have to be absolutely sure that it'll work. Just like an ASIC, in fact.
3 - The RapidChip NRE, for a device with about the same capacity as a very large Virtex-4, came in at about $100K - $150K, with much smaller MOQs. And this is a *small* device.
4 - EasyPath is not 'just the same' as the FPGA you were buying before. When I last looked, it was a device that had failed test. Perhaps someone from Xilinx could comment on whether this is true or not. This matters, because fewer devices will fail testing when yields go up, as they will. You're going to have to ask yourself whether Xilinx will carry on selling you cheap devices when they could sell them to someone else at full price.
5 - As I said in my other post in this thread, there is no comparison between EasyPath and even a 'structured' ASIC when it comes to capacity, performance, and power consumption.
6 - You can (or could) get RapidChip prototypes in about 8 weeks from handoff. I don't have EasyPath figures, but it's not going to be a lot less than that.
7 - I've seen (in several places) the claim that EasyPath devices are cheap because they require less testing. I don't believe it. They're cheap because they failed test in the first place, and so would have no value at all without the EasyPath route. It would be nice to have a definitive statement from someone in Xilinx if they happen to disagree with this.
Where I agree with Austin is "I do not consider Easypath as a competitor to ASICs". So, what on earth is the point of spending all this (uninformed) effort knocking ASICs? If someone can get the business model right, then Structured ASICs will fit very nicely into the space between FPGAs and standard cell. And they will make no difference at all to the vast majority of the FPGA market.
First, I would like to see the Xilinx take on these items as well. Although I fell I "know" the issues, it's nice to have reassurance.
Comments below:
At a structured ASIC presentation, I railed on the guy that said that Xilinx was selling bad parts. It's been underscored here before that the parts are
*not* rejects from the main testing that get shoved over to the easypath line in the same sense as harddrives with bad sectors that didn't need "those" sectors. The parts are UNTESTED to begin with, have a yied% chance of being a 100% good device, and are *guranteed* not only for your explicit bitmap but for 100% LUT operation as well. 100% LUTs are good. 100% of the routing and resources you need are also good. If you have an error in the silicon, it doesn't burn a hole in your board; an unused feature or routing segment doesn't work which is inconsequential. Keep in mind that devices with redundancy have MANY chips that are shipped with KNOWN defects that are just "programmed out." *IF* you have a defect with EasyPath, it won't screw up the design that you submitted to them for 100% testing.
I worked at a company that produced a high-end piece of test equipment as well as a low-end box. The difference in the hardware was *minimal* but we opened ourselves to a market that required mininal NRE. The development for the big box was already bought and paid for. We still made a decent profit on the lower-cost box but it wasn't quite the margin of the more expensive brother. The margin we lost was made up for in reduced NRE costs up front. It's great when you can make *more* money by expanding your market without losing your base.
It's *quite* probable that Xilinx doesn't save the cost difference between a production FPGA and an EasyPath FPGA with just the savings in test time. It's likely that they take a lower margin on the devices to keep customers who might change to a lower-cost, higher NRE solution by lowering their margins. They still make money. They don't need to provide the support and development to support 50 1k/yr customers compared to 1 50k/yr customers. Xilinx gets more profits. Customers get less costly solutions. The only folks left out are those that had alternative paths to offer beyond the Xilinx flow.
My thoughts, my opinions. I like the business case.
Nope. We ask that folks are serious. Just like for ASICs. Don't want to waste our time on non-real requirements.
Not true: you may change any LUT contents that you already are using, and you may change any IO standard on any pin you are already using. There are other changes which are allowed. Try that with an ASIC! We call it the ECO capability of EasyPath (some stuff we have to test 100%, so you benefit).
RapidChip? Oh those guys that just left the business? Oh well. I could offer you gasoline at 8 cents a gallon, and I am sure I would have a long line at my station...
Not true: it is a device that is only tested for what you need.
Commonly asserted by others to apply FUD. This matters, because fewer devices will fail testing when yields
We will start wafers just to meet EasyPath. It is that cost effective. And, we do just that.
Ohe really? I think one can comapre them. Some areas (like leakage) the ASIC will win. Some areas (like 10 Gb/s MGTs and a PPC, and a TEMAC) the EasyPath will win, as these IPs are not even available all together in 90nm!
Yes. Except that now, RapidChip will arrive "never." When EasyPath arrives, there is nothing to do, but plug it in, and ship it. No requalification is required: there is NO DIFFERENCE in what goes in the socket. Re-qual costs can be substantial, and the re-qual can take months...
Well, I can't convince you without desrcibing why. And in describing why, I will educate you. And I have no incentive to do that. You may look up the patent if you wish. They're
Definitive statement: testing a product for one use saves an incredible amount of money. Look at ASICs....
Oh, I don't know, sounds like you learned something today? And, you and I agreed on something. Not a bad result for a thread.
The "make it your ASIC" program is selling Spartan 3 90nm part directly against gate arrays (an easy winner, no brainer), and selling Spartan 3
90 parts directly against a segment of the standard cell ASIC business (definetly can't win all of that market! - yet).
In fact, the "make it your ASIC" (referring to Spartan 3 90nm) has been so successful, that with 10 million devices sold (see press announcement), it represents more 90nm, basically supplying 70% of all
90nm FPGAs.
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That was December, 2005. And now we have had almost a whole quarter of sales which just extend this lead by even more (which I can't say, as I really don't know the numbers until they are announced).
How does that compare with 90nm ASICs? Well, I can say pretty safely that without this program, and these parts, there might be 10 million more 90nm ASICs in the world in the last year...
But I really doubt it, as most ASICs don't work, never get to market, and generally just cause gray hair.
Wow - and I have to smile again... :) Now you are saying that 100% of the Spartan 3 business is ASIC replacement, and that a spartan sold is an ASIC replaced/removed ?
Many companies have 'bining' flows, where the same die attract different prices, sometimes over a 2:1 range.
Yes, EasyPath helps if they can use otherwise reject parts, but remember if it failed a generic test, it is likely to fail in your application. ie Only a subset of failure types will be candidates.
Testing IS expensive, but so also is running a custom test - thus the fairly high NRE prices on EasyPath - it also serves as a 'go away' flag to those with insufficent volumes :)
Testers themselves are expensive, if your app can run on a low cost one, that frees up the cutting edge ones, for higher margin full FPGAs
I'm really having great difficulty trying to understand why you think the ASIC/ structured ASIC market is going to die. Can you give us Xilinx's roadmap/business model that will compete?
For instance: can you give me a 60k/annum pricing for a product that has a
3yr life--total pcs 180k of a 375k Gate device with 3Mbit of on chip ram and
4 PLL's? And I'll compare it to my quote from our ASIC vendor. When we started this design we were in a V2PRO30, since then our design has grown beyond the limits of this device. But since I only have pricing on the V2P30 my math will have to be based on this part. I will only give percentages as it would not be prudent for me to reveal the actual numbers.
The ASIC is 8x cheaper than the V2P part. How much more lower would the ASIC be when compared to an FPGA that could hold our current design? It is very easy to see that we save the company BIG $$ by going to an ASIC. The structured ASIC pricing was approx 4x cheaper, which is still very much cheaper than going with an FPGA.
Xilinx has decided to ignore this market, based on one of your posts--155M is too small for a 2B dollar company. Altera is not quite as large as Xilinx and perhaps those dollars seem more attractive. Or perhaps Altera is using their Stuctured ASIC program to pull in other FPGA businees that they would otherwise not have: get in the door with the HC program and hope that you can pull in some future FPGA business??
Don't forget Xilinx have a (large) vested interest in talking down any ASIC MASK flows.
Did you get a Hardcopy II price from Altera, or is that what you mean here ?
Do you have any current consumption ratios ?
That has to be a very hard number to quantify reliably - for example, I doubt if Altera's HardCopy is in that pigenhole, they will be called FPGA's. Altera only has to hit ~15% revenue via HardCopy, to equal that number.
Another way to approach this, is the FSA just said their members hit $40B last year, and they are only a portion of FAB runs. TSMC alone is presently close to $10B/yr, at the FAB end.
Everything a FAB makes, is an ASIC - a large chunk will not be reachable by FPGAs due to sheer low power, or Analog features ( tho Actel can start to argue on that last point, at least for average analog features ).
We've just come thru one of the largest and longest tech slumps that has created MANY corrections and changes in the market. What has been not so profitable for the last five years is no indiction of what will be profitable for the next five years if we resume a normal boom cycle at this point. Cashflows have been VERY tight, making NRE's very difficult to swallow, which is certainly been tough on both the ASIC industry and all capital intensive related markets.
Xilinx has substantial reasons to gain by declaring the ASIC markets dead, FUD to help push projects thinking about the NRE's to FPGAs. High end businesses sift thru technologies ranging from pure ASIC to PLD on a project by project basis, directly coupled to sales ... which if headed up will also mean they are headed up the logic food chain too.
In fact, I stated the dollars are increasing (on fewer design starts).
I am stating that the structured ASIC business has been a real money loser for the companies that are toughing it out. And, that there are companies leaving that business because "there is no money" (Toshiba's quote, not mine).
So, do not misquote me. ASIC's $ increase; structured ASIC $ ? (unknown if it will increase or decrease, but you may be sure that companies will have a hard time making money if they continue to pretend it is a one or two mask operation).
155M$ is the whole MARKET (IN 2005, ISuppli). That was spread over as many as 12 companies in that year. LSI had the largest share of that, at 35M$. Everyone one else had a smaller chunk that 35M$.
Now, I ask you, if you had to assign dozens of IC Designers, software, and support people (perhaps this number is in the 100's) to support a business, how hard is it to do an ROI?
One must have assumed that the entire market was just going to explode, or the market was going to shake out quickly.
I can understand optimism. I can not understand believing that one could get even 50% of any market with so many competitors, and so many BIG competitors (IBM, Fujitsu, Toshiba ...).
I can see a BIG company making a ten year effort and realizing that the payback may not come for a long time, but even then, there is a board of directors, and that board has got to be pretty ugly right now. Wouldn't want to be in those board rooms explaining why the new star (Structured ASICs) are still losing money, and why they are draining resources, and knocking the gross margins down.
So, a simple review:
ASIC business = really HUGE $ and increasing. Design starts slowing, and reducing due to equally HUGE NRE, and issues with ultra deep submicron technolgy leading to expensive failures (or too many million $ mask sets).
Companies making business decisions to no longer use ASICs (losing too much money, time, etc.).
FPGA business picking up lots of what used to be ASIC business.
ASIC IC designers looking for jobs (we are hiring, send me your resume).
ASIC IC designers taking jobs designing with FPGAs.
Structured ASIC business looking shakey. Were 13 players. Now ten. Largest just threw in the towel.
Prices were from Altera and Rapid Chip. And both vendors came back with similar pricing. The ASIC is being done by KLSI. KLSI's NRE was also very reasonable.
No, I don't have this information presently at hand.
Misquote you? I took your comment about circling the drain to mean that it would only be a matter of time before the remaining players would bow out of the business. What else could circling the drain mean? My post was not meant to address the "time" part of your quote; but rather question what is it about the current market environment that would cause this flushing of the remaining players. And what is in Xilinx's future roadmap that would help facilitate this flushing, oh I'm sorry I mean cleansing. Because, currently, for products with large numbers, FPGA's are too expensive and don't offer the same performance. What I think I missed was that you're referring only to the structured ASIC business, and not the ASIC.
I would tend to agree that the future of the structured ASIC business is a bit nebulous. Especially after receiving the numbers on our latest RFQ submittals. The NRE on the ASIC was surprisingly competitive with the structured ASIC path. About all the structured ASIC offered was a quicker delivery by approx 3-4 months.
I'll keep you in my rolodex if indeed your premonition comes true!
Point taken. On the other hand, though, how much useful fixing can you do by changing LUT contents?
You have missed my point, which is that your perception of NREs is incorrect (and, by implication, that yours is out of line). LSI have not, AFAIK, withdrawn RapidChip because its NRE was too low.
Leakage is irrelevant to me. On my current device, the structured ASIC wins hands-down on capacity, performance, power consumption, and unit cost, as I said. Your implication that my client is incapable of trading off these factors against NRE, delivery schedules, and risk is surprising. That's what we all do in this business, every day. You have your sweet point; the ASIC vendors have theirs. Don't knock it.
How many ASIC vendors have you checked for this stuff? And did you repeat the comparison for other processors?
Ok, so I'll educate you instead. Xilinx runs at gross margins in the range of 62 - 66%. What that means is that, of every $ I pay, about
35% goes to the fab, and 65% goes to Xilinx. The test is included in that 35%. How much does silicon test cost? Real figures are hard to come by, but a figure of about 10% of silicon cost is generally used. If we're generous, and allow you 20%, that means that only 0.2 x 0.35
- ie. 7c - of every customer dollar goes on test. Of course, you still have to test EasyPath. Let's say that you save 50% of test. This means that the maximum discount that you can offer for a half-test scenario is 3.5%.
So where do your claimed figures of 30% - 80% savings come from? The numbers don't add up. You could try to claim that you offer EasyPath only on your more profitable lines, or that you cut gross margins for EasyPath products, but I don't buy it.
So, EasyPath devices are *not* cheap because they require less testing; that much is obvious. In fact, there are two ways to look at this:
1 - If the devices actually *have* failed initial testing, and there is a widespread view that they have, then you can offer a large discount because anything is better than nothing;
2 - They're not cheap in the first place, because of the NRE costs. However, we'd need some real numbers from you to decide if this is true or not.
No, it doesn't. If the silicon cost you *nothing*, then the biggest discount you could offer would be 35% before eating into your gross margins. And I can't believe that you do that, or that the silicon costs you nothing. Oh, and the unit cost advantage of ASICs has nothing to do with reduced testing.
It's been some years since I was a regular here. However, I do remember that the only Xilinx employee on c.a.f at that time was always courteous and well-informed, and didn't indulge in marketing.
There's certainly a general impression that the parts have failed test, whatever has been said on c.a.f. I'm pretty sure that I read this in Xilinx literature a couple of years ago, but I can't find it now. I may be wrong.
If this is actually the case with Xilinx, then it wouldn't be unusual (or even "bad"). It used to be fairly common to buy memory devices which had failed test in only a part of the die, and I've done this myself. No-one has a problem with this; but, of course, supply will disappear as yields go up. And I didn't have to pay NREs for them.
The other thing you have to look at is the economics. If these are good dies, then why are Xilinx selling them cheap? Have a look at my gross margin argument in my reply to Austin's post.
And if it costs me X to see if the die is 100% good, and I only spend
1/4 X to see if it works for you, then my gross margin is higher, or I can charge less and keep the same gross margin if I test for you, and no one else.
The Easypath flow is patented as a business method.
The NRE is to develop the special test program to test just for your requirement, and to handle all the overhead of a new marking, new part number, etc.
If they didn't even charge enough for the overhead in the structured ASIC business, no wonder they are all going broke while they ship their
150M$ a year (basically they wrap money around each part shipped).
Many people think that if we find a part is bad, we know what is bad: that is not true. It costs a small fortune to identify any failure, on any part. That is called failure analysis, and requires a whole team of engineers working by hand. We do that on occasion, but try to avoid it at all costs. Failure analysis is done for yield issues, and design issues: not for a bad memory cell on one part!
Another way of saying this is if I run test program "A" and I fill bucket for customers, and then I go to test program "B" and fill buckets for cutomers, and then go to test program "C" and take all parts that failed "A" and "B" (as well as new completely untested parts) and fill buckets.
Did I care why anything failed "A" or "B"? No, I do not. All I care is that it passes "C". How does this affect reliability? Not at all. We have done reliability and qualification studies on Easypath (no different that what you do for any ASIC, ASSP) that prove that Easypath has perfectly acceptable reliability and life. These die had to meet the same defect density requirements as regular product, and they had to meet all other process requirements, so they are no different that any other.
I direct you to read about LCD display "bad pixels." It turns out that all those beutiful displays we buy have some bad pixels. How many? Sometimes as many as 12 bad pixels are allowed, and they ship the display.
Do you care?
12 out of 1760 X 1024 X 3? As long as they are not in a row, or in a cluster (read: as long as the application doesn't care) the display is perfectly "good." Easypath is one better. We prove that there are no faults that are visible.
Austin
Note: all figures above are merely examples of how Easypath works, and not actual numbers (which turn out to be much more atttractive). Also the test flow is not what we actually use, but an example of > Evan Lavelle wrote:
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