1. Home
  2. Field-Programmable Gate Arrays
  3. Floorplanning with only usage estimates. Is it possible?

Floorplanning with only usage estimates. Is it possible?

I posted the jist of this on the Xilinx forums, but thought I might get a quicker response through here... ________________________________

I recently joined a large company, and my first assignment while familiarizing myself with our imaging algorithm entails drawing a very rough floorplan of a design that ultimately will consist 3 modules of code (code will also be designed by two other companies). The PCB will then be re-laid out around the FPGA (definitely a board spin at this point).

I have only received projected estimates on resource usage from the two other companies. I could probably convince them to shoot over more info, but I am certain they aren't close to finished with the coding. My team's code should eat approx. 30% of the resources on a Virtex-II XC2V-6000. I can easily obtain the HDL for this section.

To be frank, it's been a while since I worked with FPGAs and from toying around with ISE, I feel like I can only manipulate a floorplan after place and route. However, this doesn't make any sense to me b/c I feel floorplanning ideally should be performed during development.

Would someone point me in the direction floorplanning w/o code? Any feedback is appreciated.

Royce

Reply to
Roy-be
Loading thread data ...

very

will

two

I

By floorplanning, do you mean picking a pinout? That should be relatively easy - in fact, using a Virtex-II or newer device, I'll bet there is a decent chance you could live with your current pinout(your first paragraph seems to imply that there is an existing PCB with the device in question on it), due to the incredible routing resources in the Virtex-II and newer devices. This is especially true if all three teams do a good job of pipelining their designs.

Or... were you actually referring to making an educated guess where individual LUTs and FFs will go? Perhaps others would have a different take on it, but it seems to me that this would be quite a challenge without a high percent of the code completed, and I'm not sure what the quality of the floorplan would really be (ie, how close it would match what ends up going to production).

Have fun,

Marc

Reply to
Marc Randolph

Area constraints maybe? Allocate a suitably large (from best known information) rectangle to each module, and make "the module will fit within this allotted area, n * m slices" part of the module specification.

If single rectangles don't work for you, then multiple rectangles may be used, BUT the tools seem best equipped to fit one rectangle per module, so allocate each new rectangle to one sub-module if oyu have tobreak up a module in this way.

Then you can try the area constraint approach with this section and see if it fits well within the estimated area and meets timing.

Floorplanning certainly works better after P&R, but you can draw area constraints and save them (as an UCF) earlier in the design.

- Brian

Reply to
Brian Drummond

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.