In wanting to gain a greater understanding of routing options (particularly as related to making floorplanning decisions) I find myself studing devices in the FPGA Editor. One question that occured to me is: How accurate a representation of the actual device layout does this tool provide? Example:
I'm looking at an XC2V100-4FG456. I see that all embedded multipliers have the I/O on the left side only. Obviously all PIP's are on that side as well. And there are four switch boxes that would seem to be the best place to connect in/out of the multipler. These switch boxes, in turn, would be the way to access the CLB's to the immediate left and right(through their own switch boxes). Double interconnect lines seem to be the best possible path.
Are these accurate representations of the geometry? Accurate enough to decide, for example, that the path from a multiplier, through its switch box, via a double line, into the CLB to the left is slightly faster than using the same double line to go to the CLB on the right?
Can any sort of assumptions be made in terms of ps per unit length from what is seen in FPGA Editor? What's the cost (delay wise) of going through a PIP FET?
Is this the wrong approach to making floorplanning decisions?
Thanks,