Floorplanning Literature

Any good floorplanning literature (papers, books, etc.) ? I'm needing it for floorplanning FPGA architectures (Spartan 6), but any general text about the subject would be cool. I already read fliptronics's introduction.

Reply to
Leo
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I don't know of any docs relevant to floorplanning other than what you might find at the Xilinx site. Floorplanning is not easy to use effectively in my experience. The one project where we really needed floorplanning I found it to be nearly impossible to use. That was in an older Altera part using MaxPlusII. That tool was not so easy to manipulate as the Xilinx tools I expect.

Why do you need floorplanning? What do you expect to achieve using it?

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Rick
Reply to
rickman

PlanAhead (now part of Xilinx tool chain) was developed by a company called Hier Design. It's likely that they had some significant white- papers on floorplanning.

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Gabor
Reply to
GaborSzakacs

t for floorplanning FPGA architectures (Spartan 6), but any general text ab out the subject would be cool. I already read fliptronics's introduction.

I have a really tight design on resources (primarily carry logic and DSP, L UT and Regs are around 63%). I was expecting to up a 50Mhz design into a 10

0Mhz by overriding some of the placement done on map. The design is heavily pipelined, but the external memory interfaces are among the critical paths . The design needs to access one memory for reading and another one for wri ting at the same time (on opposed banks), and then when an internal 'cycle' finishes, switch the role of each memory. The main problem is that when I floorplan it to achieve better timing (placing memory accessess in the mid- point between opposed banks), the routing becomes heavily congested and doe s not complete. I'm assuming that happens because there are signals running vertically when memory accesses are being done horizontally. In the end I think that I will have to reduce the resource utilization to achieve timing , I mean remove a few parallel and independent pipes (with the performance hit that it means).
Reply to
Leo

I can't find any, the only thing I found was the Acquisition of Hier Design by Xilinx.

Reply to
Leo

I'm not totally clear on all the details which can be important as there are more than one way to skin a cat. I think you are saying you have two memory interfaces which you are running in parallel. These memory interfaces are on the left and right sides of the chip so you have the control logic in the middle. Is there a reason why you can't put the memory interfaces on, say, the top and right to make them closer together and to potentially move the routing out of the way of the other logic? Or has your PCB been laid out?

The problem you are seeing with floorplanning is exactly the sort of thing that can happen. While the tool may not understand your design, it understands the limitations of the chip. With the designer this is reversed. You are hitting a wall with the chip resources.

So maybe don't floorplan for this problem. Can you add more pipeline stages? It is not unreasonable to add pipeline registers to break up the routing delays. No logic, just an extra FF in the paths that are giving the most trouble.

Or maybe not floorplan the entire block of logic in one spot. Would it make sense to spread it out horizontally a bit which might leave some space for the vertical signals to weave through?

But then 100 MHz is not all that fast. Have you looked at the details of the slow paths? Do you understand where the tool is having trouble meeting the timing goals?

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Rick
Reply to
rickman

it for floorplanning FPGA architectures (Spartan 6), but any general text about the subject would be cool. I already read fliptronics's introduction.

an

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P, LUT and Regs are around 63%). I was expecting to up a 50Mhz design into a 100Mhz by overriding some of the placement done on map. The design is hea vily pipelined, but the external memory interfaces are among the critical p aths. The design needs to access one memory for reading and another one for writing at the same time (on opposed banks), and then when an internal 'cy cle' finishes, switch the role of each memory. The main problem is that whe n I floorplan it to achieve better timing (placing memory accessess in the mid-point between opposed banks), the routing becomes heavily congested and does not complete. I'm assuming that happens because there are signals run ning vertically when memory accesses are being done horizontally. In the en d I think that I will have to reduce the resource utilization to achieve ti ming, I mean remove a few parallel and independent pipes (with the performa nce hit that it means).

Yes, I have memory interfaces in the left and right banks, but also one in the top bank (PCB is done). The third memory interface is NOT needed, so I can exchange banks at will. With the top and right memory banks and no floo rplanning at all, ISE succeeds in implementing it at 50Mhz, but not more. T he critical path is between the memory banks, since the access is in the mi d-point of both (the tool did this automatically), the complete delay to ei ther bank is close to 20ns. A level of pipeline will surely help, and it is in the works. I was trying to use left and right memories to ease the timi ng without pipeline, but this evidently complicated the routing. So, a comp romise must be made. I think that's all for this project. Thanks for your o pinion.

Reply to
Leo

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