Hi I am working on some Spartan3 projects using ISE8.2 on WindowsXP.
One of the designs (XC3S4000) instantiates a core from a 3rd party as an EDIF netlist. I then add all sorts of other home spun blocks around it.
I am quite happy with the core's function, and am now just adding peripheral blocks and debugging them etc. This is proving frustrating due to the Xilinx tool ripping up and re-routing the whole design each time I compile. It takes 1.5hrs to recompile, which may not sound a lot, but to add a wire is a bit ridiculous IMHO.
I would really like to fix down some of the blocks to stop the Xilinx tool re-placing etc.
At first glance there seems to be many options in the Xilinx tools to do this, but I can't get any of them to work properly. So far I have tried the following: - Partitions. They don't work >at all< do they? I can't even add one and get it to pass through MAP. - Incremental Design Flow, I don't seem to be able to get ISE to use my area constraints, and how do you find out how big to make blocks in floorplanner? - Planahead. Beta, poor doc's, didn't know where to start really. Even my FAE doesn't have a scooby-doo about this one. - FPGA Editor Does anyone use the probe points to debug? I don't seem to have anywhere near a full netlist to choose from, even if I don't flatten
So questions to experienced ISE users;
1) How do you tie blocks down? (or do you not bother?)2) Are the 8.2 service packs an improvment? I briefly tried pack2 a couple of weeks back, but it destroyed one of my projects so I couldn't load it into a non SP version on another PC. Obviously backwards compatibility is not high on Xilinx's lists.
3) Does anyone use Floorplanner? Are there any GOOD tutorials out there?Regards Marc