I am new to verilog/hardware arithmetic and seeking good advice on testing a fft butterfly stage that I have written.
module butterfly #(parameter size=16, Q=4) (input signed[size-1:0] a_real, input signed[size-1:0] a_imag, input signed[size-1:0] b_real, input signed[size-1:0] b_imag, input signed[size-1:0] w_real, input signed[size-1:0] w_imag, output reg signed[size-1:0] x_real, output reg signed[size-1:0] x_imag, output reg signed[size-1:0] y_real, output reg signed[size-1:0] y_imag ); reg signed[size-1:0] w_b_real; reg signed[size-1:0] w_b_imag; always @(a_real or a_imag or b_real or b_imag or w_real or w_imag) begin
w_b_real = b_real*w_real - b_imag*w_imag; w_b_imag = b_real*w_imag - b_imag*w_real; w_b_real = w_b_real >> Q; w_b_imag = w_b_imag >> Q;
x_real = a_real + w_b_real; x_imag = a_imag + w_b_imag; y_real = a_real - w_b_real; y_imag = a_imag - w_b_imag; end
endmodule
When writing the test bench, I came across several problems which I have no prior experience.
- How to create fixed point signed numbers that can be fed as input which will not create overflows inside butterfly module
- How to create the expected results to compare
Greatly appreciate any help on these regard.