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fixed point dot product with log2(n) pipe stages in vhdl

I would like to write a parameterizeable component in vhdl that would do an N element fixed point dot product. I was wondering if there was a (synthesizable) way to generate a first stage of multiplies (ceil(N/2) multiply blocks), and then ceil(log2(N)) - 1 add stages. I would like to be able to use generics to specify the length of the vector and the bit width (this in turn specifies the length of the MAC pipeline).

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Geoffrey Wall
Masters Student in Electrical/Computer Engineering
Florida State University, FAMU/FSU College of Engineering
wallge@eng.fsu.edu
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geoffrey wall
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Forgive my ignorance and/or stupidity, but how can you get away with only N/2 multipliers and logN adders? Is there something special about the values you're processing, or is there some cool math I don't know about?

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Jonathan Bromley, Consultant

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Jonathan Bromley

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