The FpgaC internal algorithm is pretty generic, and just decideds pretty early on to force all internal functions to 4-LUTs. This makes it difficult to decide to use support logic like H-LUTs on XC4K, or F5 muxes on Virtex parts, or the carry logic on any of these.
I'm looking for papers which discuss/descript alternative fitting algorithms to better use vendor assist logic in FPGAs, particularly for scheduling logic expressions across multiple LUTs for both space and time specific tradeoffs.
Totally_Lost schrieb:
Probably the most important thing is to recognize all addition networks and map them to carry logic. You can do this in a preprocessing step. I think there is a paper by Stoffel/Kunz/Wedler on identifying arithmetic elements in gate level netlist. Alternatively you can preserve that information from RTL.
H-LUTs with inputs independant from the F and G LUTS are not even supported by Xilinx software. Not even if you instantiate hardmacros. I suggest that you handle the H-Lut as a F5 mux. No use to put to much effort into obsolete hardware.
The problem is that with special cases you kill the nice properties of the flow map algorithm. You need to experiment wether your optimal 4-LUT result is better or worse than a heuristic result for 4-LUTs plus muxes. Supporting a mix of 4, 5 and 6-luts using the muxes can probably done quite elegantly but this leaves out all the wide input functions.
Kolja Sulimma
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