FIR in FPGA

Hai,

1.Can i set the clock frequency of the FIR filter at any frequency i want... but pretty much higher than the sample rate? for example :Fc=3.5khz Fs=8khz can i clock as any value >8khz say 1Mhz(considering the max clock for target device)

2.Whether direct form non-symmetric filter structure can support symmetric coefficients??whether the response computed in non-symmetric structure is same as symmetric filter structure?? I knew resource utlization wise symmetric need more adder at the cost of multpliers..

3.In addition to impulse test(basic test to check FIR filter operation before implementing to FPGA),step test,sine wave test.What are other test that has to be compulsorily performed in time domain to check the proper working filter operation before giving any arbitary input to the filter??

regards, faz

Reply to
fazulu deen
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Let me try to respond with some questions of my own.

Are you familiar with the concept of "clock enable"?

I assume you understand the phrases you have used in the question. Can you please explain what you find hard or non-obvious about your question?

Have you considered the effects of numeric overflow in your filter?

Are you sure it needs more adders than an equivalent canonical implementation? What leads you to believe that?

Do you understand the concept of linearity? Can you think of anything that might make your filter non-linear? (Clue: my previous question about overflow). Do you trust your adder, multiplier and register building blocks?

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If you are simply reproducing homework problems, please do us the courtesy of trying to solve them yourself before asking for help. If these are real problems of understanding, then please give us a clue about what you already know and what you find difficult.

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Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

hai,

Are you familiar with the concept of "clock enable"? yes i do..I asked during implementation wat is max clock frequency can i set for the example pointed out by me...

Can you please explain what you find hard or non-obvious about your question? I mean structural difference and coefficients support between symmetry and non-symmetry

Have you considered the effects of numeric overflow in your filter? For response checking (during testing)i will consider that...

Are you sure it needs more adders than an equivalent canonical implementation? What leads you to believe that?

Have you ever seen the symmetric and non symmetric structure structure before once u see u will also believe in it..

Do you understand the concept of linearity? Can you think of anything that might make your filter non-linear? (Clue: my previous question about overflow). Do you trust your adder, multiplier and register building blocks? yes i do..critical path might make it non-linear....

if these are real problems of understanding, then please give us a clue about what you already know and what you find difficult. my problems are mentioned as questions and few comments about the currents progress to get the answers from the group..

regards, faz

max

Reply to
fazulu deen

FIR filters can (in almost all applications) be pipelined as deeply as necessary, so the upper limit on clock frequency is much the same as you would get for any other logic in the same technology. All that's needed is to enable all the FIR's registers for one clock cycle on each sample (i.e. at the appropriate sample rate). Not hard.

I asked...

I know how to build an N-tap non-symmetric FIR using N multipliers and N-1 adders. And I know how to build a symmetric or antisymmetric N-tap FIR using ceil(N/2) multipliers and N-1 adders (some are subtractors, if it's antisymmetric). So I don't see why you think you need extra adders in the symmetric/antisymmetric case. Do you know some additional tricks that I don't?

My point is this: if it's truly linear, and it gives the correct impulse response, then it's correct; no further testing is needed. However, nonlinearity could easily be introduced by... - buggy multiplier or adder blocks - arithmetic overflow - improperly connected input bits that were not exercised by the impulse test

I'm none the wiser.

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Reply to
Jonathan Bromley

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