1. Home
  2. Field-Programmable Gate Arrays
  3. FIR Filter ON FPGA

FIR Filter ON FPGA

Hi, I'm working on implementing an FIR Filter on a FPGA (Spartan 3E), here's what i want to accomplish -->

The FIR Filter coefficients are generated on a host system using LabView, these coefficients are written to a RAM / PROM on a DSP card , the number of taps is constant but other parameters like sampling frequency and cut off frequencies can change according to requirements.

The FPGA reads these coefficients from the RAM / PROM and implements the FIR Filter.There should be a single bit file that is downloaded to configure the FPGA.

Any pointers in the right direction would be appreciated.

Thanks Tim

Reply to
bngguy
Loading thread data ...

It is (probably) easy to have the DSP download the coefficients into the fpga through some serial (SPI-like) interface. An SPI interface can consist of a counter generating the bit addres (BRAM in 1 bit mode on the configuration side). The SPI clock can be the clock for the counter and the memory, the SPI select resets the counter and disables writing to the memory when low.

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl
Reply to
Nico Coesel

Hi Tim,

Use the core generator in ISE and select Distributed Arithmetic FIR. This core enables to modify coefficients on the fly - during operation. You just need to have some kind of interface to download this coefficients (serial, parallel, SPI...).

Cheers,

Guru

Reply to
Guru

Hi Tim,

There's two halves to the question. The first is getting the coefficient values into the FPGA, and the second is creating/using a FIR structure which allows for coefficient reload.

There's a new FIR filter design tool which creates clear text human readable Verilog based FIR filters (which can be synthesized to Spartan 3 with Xilinx ISE) with a coefficient reload option.

If you want, you can also store multiple coefficient sets in the filter without having to reload them, and simply switch among the various sets (this works well for deeper memory, ie: store several sets on-line and switch among them).

Anyway, here's a link :

formatting link

Hope this helps,

Tony

Reply to
tsan

It looks like you'd like to quickly easily reload or change coefficients in a FIR filter (so you may want to just load in the coefficient values into a multiplier based FIR filter, rather than have to generate ROM LUT values to load into a distributed arithmetic FIR filter).

There's a new tool which creates clear text human readable Verilog code for FIR filters (which can be synthesized into a Spartan with ISE). Options include reloadable coefficients as well as multiple coefficient sets. There's a self checking testbench with impulse, step and random response.

You don't mention how fast your computation rate is, but this tool supports single or multiple clocks per computation (so you can decrease your multiplier usage).

Anyway, here's a link :

formatting link

Hope this helps,

Tony

Reply to
tsan

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.