That looks right. Each product (input*coeff) gives a width of (input bits) + (coeff bits). Assuming all your coefficients have that same width, your maximum output value cannot exceed N*(max_input*max_coeff), so giving a bit growth of ceiling(log2(N)) over the output width of each multiplier. Early stages in the pipeline obviously can use narrower words.
In the systolic form (input fed to all multipliers simultaneously) and assuming coefficient widths are the same for all taps, the sum's bit growth at each tap is:
Looks like someone's assuming the coefficients and input are the same width, doesn't it?
FIR filters are really rather easy to reason about. At each step you can easily pre-calculate the largest possible numeric value that can be seen. You may be able to use knowledge of the input stream to set even tighter bounds on bit width, but the benefit is rarely worth the hassle.
IIR filters, of course, are much harder.
Try comp.dsp where there is some very heavy-duty filter expertise. (There's plenty of filter expertise here too, mind you!)
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Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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