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Filtering the FPGA reset signal

Hello,

On my board, the FPGA receives its reset_n signal from a voltage supervisor IC (such as MAX635x or LM370x).

Is there a point to further filter (digitally) this signal upon entry into the FPGA ? Does this improve or reduce the resiliency of the design to errors / glitches / noises ?

In favor of filtering: glitches on the line between the voltage supervisor and the FPGA will be filtered.

Against filtering: (1) enforces synchronous reset, while I might want it to be asynchronous. (2) ignores a valid reset signal from the voltage supervisor when the supplies "go nuts" for the filtering time, which may lead to undesired results.

What are your thoughts ?

Thanks in advance

Reply to
Eli Bendersky
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Hi Eli, You don't need my thoughts, especially at this early hour! Luckily, there are plenty of other thoughts easily available. :-)

Google:- reset synchronous site:xilinx.com

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HTH, Syms.

p.s. We've been over this many times on this newsgroup before. You'd do well to trawl the archive.

Reply to
Symon

I think you misunderstood my question. I am not asking about a synchronous vs. asynchronous reset and about reset release. I'm asking about filtering potential noise that may be present on the reset_n line on the board that goes between the voltage supervisor and the FPGA.

Eli

Reply to
Eli Bendersky

If you have some reason for suspecting that the reset_n signal is noisy then you should address that with board level changes to get rid of the noise source.

If your FPGA and board design happens to have a single clock source then synchronizing the incoming reset signal to that clock before distributing it anywhere would make the design somewhat more immune to ground bounce of the chip relative to the plane since the reset signal would only be sampled at the clock edge and the I/O switching which causes the bounce will occur after that edge. If you don't happen to have this special case though then you'll need to deal with the noise source directly as I mentioned.

I'm suspecting though that the reason for the question is because you think 'reset_n' is such an important signal that some form of noise filtering should be done. That reasoning though is flawed. I'm guessing that there are probably very few inputs to your FPGA design that could tolerate noise to the extent that the logic level gets misinterpreted. Reset just happens to be one of your inputs, what about noise on any of the rest?

KJ

Reply to
KJ

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