Files produced by Quartus II compiler

Hi,

I'm a student using Altera Quartus II v6.1 to program a Cyclone II on a DE2 development board. I'm starting to build a library of Verilog modules to re-use in future projects (mostly simple things like adders, flip-flops, etc. - I don't want to use MegaFunctions too much to avoid getting locked into Altera products) and I was wondering the best way to do this. I notice that, when I compile a project with a library folder (containing another project for, say, an adder), I get a warning that the compiler is using abc.v (or whatever the verilog file is called) as a design file although it is not included in the current project - which is what I want it to do. However, this implies that it is "compiling in" abc.v into the current project, which seems a waste.

So... is there an equivalent of "object code" in C++ that I can include in my projects? So, for example, I could compile my full adder module, copy some file (not the verilog code, but a compiled/partially compiled binary file) into my library folder, and then use it in future projects without making Quartus recompile it.

Based on file size, I'd say the *.sof file is the best bet, but I haven't found any information as to what this file is for. In any case, I'd like to know what all the other files are for (apart from the *.rpt files, which I know are the reports from the compiler, simulator, etc.). Can someone point me in the right direction?

Thanks in advance, Allan Lewis.

Reply to
scouselad
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Not exactly. Synthesis converts a source code module to a netlist of vendor-specific primitives. That netlist is routed and Fmax is checked. It is possible to lock down a placed netlist but this is not without it's own annoyances.

Quartus is pretty smart about not duplicating every step on a recompile, so I just recompile. However I spend most of my time in the edit/simulate loop.

You can reuse source code modules, functions, templates etc at the editor level.

-- Mike Treseler

Reply to
Mike Treseler

In addition to Mike's comments:

The reason you get that warning is that some module instantiates (calls, for you 'C' people) a component you didn't specify in the project (link list ...). Specifically, some module instantiated abc, but i was not in you project files list. Quartus found a file 'abc.v' (in your project's search path) with a module 'abc' in it, and guessed that this is what you wanted.

There is an equivalent of 'object code', that would be the netlist. But it's not useable as seamlessly as a collection of .o files, and it certainly does not behave like a .a file. The only other parallel I can think of is a 'synthesizeable VHDL package' but that isn't much use for the Verilog crowd.

The good news is that you don't have to worry about the 'unreachable code' equivalent. All (modern) synthesizers have the ability to rip up unused logic.

And I wouldn't worry too much about the amount of time it takes to compile your code. 90% of the tool-time is (probably) place & route, and pre-compilation doesn't change this. (It might make it worse, as it does take time to trim out unused logic.) And as Mike so accurately pointed out, most of your time will be spent testing & debugging. (Personally, I use the place&route time for a well deserved coffee break.)

Gary.

PS: If you haven't found out what the .sof file is for, you have quite a bit of the basics left to cover before leaping to advanced topics. "Patience, grasshopper :)"

Reply to
ghelbig

Thanks to both of you for replying so quickly!

I definitely have a lot to learn - thanks again for both replies.

Reply to
scouselad

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