1. Home
  2. Field-Programmable Gate Arrays
  3. FIFO16 on virtex4 error?

FIFO16 on virtex4 error?

I am currently using FIFO16 with xilinx Virtex-4. I found out in my design, the "almostempty" "almostfull" "empty" "full" flags are all stay high. That means some errors happen. The FIFO16s are configured as:

width 36 depth 512 almostempty offset 12'd128 almostfull offset 12'd256 first word fall through (FWFT) Mode "True" read_clk 162Mhz write_clk 200Mhz

Is there any issues here? It's been reseted before use, (reset assertion time is more than 3 clock cycles for both read and write clock).

Anyone have similar experience or something wrong I doing. The clock speed should be OK based on performance table.

Thanks, Chao

Reply to
Chao
Loading thread data ...

Have you read this :

formatting link

Sylvain

Reply to
Sylvain Munaut

I belive FIFO 16 in V4 has problems, I can't remember exactly what they are, but I do remember seeing some app notes with work-arounds. Check the Xilinx site FAQ and you should be able to find the info you're looking for.

Reply to
bruce_hw_guy

Yes, there are known problems. The work-around is described in Answer Record 22462. You can also go to the Xilinx website and search for Virtex-4 FIFO AR. Peter Alfke

Reply to
Peter Alfke

Thanks all of you. This really let me out. I used core generator to generate a new fifo16, it solved the problem.

Chao

Reply to
Chao

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.