In my design I have one Asynchronous FIFO v6.1 that I instantiate twice.
When I simulate my design (using Modelsim v 6.0) one of the instantiated FIFOs behaves as expected (in accordance to the datasheet) but the other doesn't.
On the offending FIFO, when I assert the READ_ENABLE signal immediately the DATA is presented on the DATA_OUT signal (same clock cycle as when the read enable was asserted). However, the expected (and the behaviour of the first FIFO) is that when READ_ENABLE is asserted the DATA is presented on DATA_OUT one clock cycle later.
Does anyone have any ideas why two instantiations of the same FIFO behave so differently?
Regards,
Simon