FiFo Help Needed

im getting this error when I do my simulation with Modelsim

# ** Warning: Design size of 11167 statements or 0 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity.

in my simulation it looks as if nothing has been written into the FIFO even when I enable wr_en

Wich means that your ModelSim license doesn't allow for simulating design of such size.

/Mikhail

of

hmm so is my codes right?

gn of

or rather... how can I simulate the FIFO?

If you can afford it upgrade your license. If you can't afford it try partial simulations or see if you can find a less resrtictive free simulator, or get an evaluation license, etc..

/Mikhail

Why does it take 11,167 statements to describe a fifo? See

no idea I used the Core generator to generate and used the structural one to simulate and end up getting that error

It is not an error, only a warning. It does not prevent you from simulating the design. It only states that your license type will force ModelSim to run very slowly. However I think this has nothing to do with your problem simulating.

What do you mean by "there doesnt seem to be any data coming out of my FIFO during the clock cycles"? Can you look at the simulation and see that the data is going in to the FIFO and the write enable is active? Does the FIFO become non-empty and read enable asserted? Have you dealt with the global reset for the core model? Perhaps it's always being held reset?

Regards, Gabor

erm

i've found it I didnt expand my timing far enough to observe the data output.