FIFO design

Hello!

I meant that I need a FIFO + this special "feature" to convert the data to the right length. I thought that i could solve this problem by building a special FIFO.

How could I solve this problem?

Thanks, Simone

"Peter Alfke" schrieb im Newsbeitrag news: snipped-for-privacy@xilinx.com... : Simone, when you call this a FIFO, it makes it sound complicated and : creates fear of non-synchronous problems. But this does not seem to be : the case here. : I would just use the appropriate number of registers with the right : input muzes and a tiny state machine that makes them do the right thing : at the right time. You need to consider the required frequency or time response. : Should be quite simple. : : Peter Alfke : ================= : Simone Winkler wrote: : >

: > Hello! : >

: > I want to build a FIFO for a special purpose: : > I've got a microcontroller that interfaces to a SDRAM via an : > SDRAM-interface. The microcontrollers data width is 16 bit while the : > SDRAM-interface needs 32 bit (if i write something to the sdram, in the : > first clock cycle, the interface needs the bank, row and column address (32 : > bit) and in the second clock cycle the data (only 16 bit, the upper

16bit : > are just don't care)). : > Now I need a FIFO that converts the 2x16 bit to one 32-bit word. Timing is : > not important, only the 2 words of 32 bit have to be sent one clock cycle : > after the other. (so i don't need a "doubling" of the clock rate, just a : > method to combine the two incoming words) could it work with a kind of shift : > register? : >

: > Thank you for your help! : >

: > Simone

Simone, I was just commenting on the name FIFO, whichin some minds (including mine) paints a picture of significant depth and complexity.

In your case, I assume you just need one or two or four 16-bit wide registers with the appropriate multiplexers.

At slow speed, this is trivial. At 200 MHz, you have to be a little careful. If you want to discuss details, c>

Well said.

Thinking only in terms "well know" logic blocks can obscure the real requirements, and the real fpga resources.

-- Mike Treseler

If you make the FIFO 32 bits wide on both ports. Then alternate between writing to the lower and upper half of the 32 bit datapath on the "16 bit" side of the fifo you have effectively converted from 16 to 32 bits when travelling through the FIFO.

(32

shift

Thank you! And how can i realize a 32-bit wide FIFO? At the moment I use the Xilinx-FIFO-designs for Spartan-II. They use block ram - but the biggest module i can get is 16bit-wide. Is it possible to use 2 instances of ramb4_s16_s16 and drive each instance with the same clock, enable signals and so on?

Thank you,

Simone

"Mike Lewis" schrieb im Newsbeitrag news:4P-dnWSWl-I_ snipped-for-privacy@magma.ca... : If you make the FIFO 32 bits wide on both ports. : Then alternate between writing to the lower : and upper half of the 32 bit datapath on the : "16 bit" side of the fifo you have effectively : converted from 16 to 32 bits when travelling through the : FIFO.

I'm not sure if you can use the canned FIFOs from coregen. What you really need is a FIFO with byte write enables. You might have to design your own FIFO with this feature.

Mike

the

The problem here is that Simone never explained what she is really out to do. Is there really a need for a FIFO of significant depth, or can one just use a few registers ? Where do the 32 bit address and the 16-bit data come from, and since the other 16 data bits are don't care, why are they not just ignored ?

As long as we are being kept in the dark about the real intention, any suggested "solution" is meaningless. Sorry, Simone, for being so blunt.

Peter Alfke =============================

Mike Lewis wrote: