fifo counter in virtex-4

I use ise9.1 and synplify8.4.2,I use the core generator to generate a fifo,the parameters as follow,different clock and different data bus widths,write 16 bits and read 128 bits,now I want to use the fifo data counts to control my logic,the fifo depths is 256 for read,and I don't use the all fifo,if the fifo data conter reach 200,the logic must stop writing,the logic can't write one more or less,so i need the accurate fifo data conter,but from the datasheet I know that near empty and full the fifo counter will be not accurate but I dno't know if the fifo counts is accurate near 200(write and read will be not at the same time near 200),also under reset or power on,the fifo counts is

2(but now there are no datas in fifo,I don't know why?)
Reply to
bjzhangwn
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Dear Unsigned Poster,

I think you may have set a new CAF record. One hundred and fifty two words without a single full stop. Remarkable, especially considering your use of apostrophes, plurals and capital letters is pretty good. ;-)

Anyway, that's all well and good, but your post is, unfortunately, as good as incomprehensible. I'd guess your first language isn't English, however I'd respectfully suggest you try and reformat it, and I expect you'll get a lot more responses.

I noticed, a few days ago, a post which was perfectly crafted to elict maximum response. You might like to check it out, the subject line was "Hobbyist trying to decide which device to start with...". The guy firstly gave a brief background to his position. Then he explained his problem. Next, he posed some questions. Finally, he pointed out that he had found some solutions for himself, but wanted further suggestions.

He did this in four easy-to-read paragraphs, which showed respect and consideration for the reader. He realised that any response he gets on this newsgroup is free, and requires the responder to take the effort to understand his post. He made the post easy to comprehend.

Anyway, I hope this reply doesn't sound too patronising, I really do want to help you get your questions answered. So, good luck and HTH, Syms.

p.s. For further study:-

formatting link

Reply to
Symon

In addition to making your statement/query/issue/rambling readable, please let those who can help know if you're dealing with a synchronous

- FIFO where the input and output clocks are the same clock - or an asynchronous FIFO where the input and output clocks are different clocks.

If you have the synchronous FIFO case, my suggestion would be: build your own!

Synchronous FIFOs are easy to produce and can give you the full access and control you're looking for. If you want more than the core will give you, making your own is often the quickest route.

Reply to
John_H

As I think the previous posters have alluded to, designing your own fifo using the blkrams is pretty straight forward. The reason is that the blkrams are synchronous dual port memories ... pretty easy to implement fifo structures.

Keep a separate word_depth_counter .... increment on writes ... decrement on reads ... leave alone on cycles with both occurring.

Within the directory path /xilinx/doc/usenglish/books/docs is the document lib.pdf. Under the component for RAMB16_SN_SM is a pretty good description of the blkrams.

Anyway ... good luck.

--
Regards,
John Retta
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Reply to
John Retta

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