FF setup and hold time.

Hi, can any one please clarify me that all the FF in the FPGA has same setup time and hold time values? If not why and where these different FF can be used?

Thanks in advance.

regards, Himassk.

Reply to
himassk
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There are two different FF as a minimum - IO registers and internal logic FF. More specially look into the datasheet for your FPGA. As a rule all datasheets have separate sections for I/O timing parametres and Internal timing ones.

Reply to
cms

Why do you ask? There usually is a hidden reason behind questions like yours. Obviously CLB flip-flops and I/O flip-flops are different, as are registers in the BRAM and the DSP48 blocks. But all of these parameters are documented in the data sheet (on the web). Positive hold times have ugly system ramifications, and we try to make them zero or negative whenever possible. Peter Alfke, Xilinx

Reply to
Peter Alfke

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