Hi, I have a design that needs to stall a long pipeline (with the CE input of registers). The module receiving data from this pipeline sends a busy si gnal, that within 3 clock cycles must completely stall the pipeline. The lo ng routing delays from the end to the beginning of the pipeline cause my de sign to fail timing.
Now, since the STALL signal comes from a shift register made of (3) Flip-Fl ops, how can I get the tool to replicate this flip-flop chain, i.e. make a flip flop tree in such a way that meets timing ?
I have tried putting a MAX_FANOUT constraint to the high fanout signal, but the only thing this does is replicate the buffers. Also tried applying "Re gister Duplication" and "Register Re-Timing" to no-avail (the registers are n't duplicated, they are moved around a little only).
I want this done automatically because the pipeline can vary it's size, but I don't know if it is practical anymore.