fatal error : help required

It might be helpful if you posted line 337 of :/ACSUNIT/totalunit.vhd line 337, as well as all other lines that shed light on this line of code.

Alternatively, you could open a case at support.xilinx.com.

Or you could upgrade your project navigator to something in the 5s or

6s.

Hi, this is my code. all components are synthesizing individually.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity totaldecoder is Port ( s1 : in std_logic_vector(2 downto 0); s2 : in std_logic_vector(2 downto 0); T3 : in std_logic_vector(3 downto 0); clk : in std_logic; clk1 : in std_logic; reset : in std_logic; val : out std_logic ); end totaldecoder;

architecture Behavioral of totaldecoder is

component BMUnew port ( S1 : in std_logic_vector(2 downto 0); S2 : in std_logic_vector(2 downto 0); BM0 : out std_logic_vector(3 downto 0); BM1 : out std_logic_vector(3 downto 0); BM2 : out std_logic_vector(3 downto 0); BM3 : out std_logic_vector(3 downto 0)); end component;

component comparatortreenew port( k1 : in std_logic_vector(5 downto 0); k2 : in std_logic_vector(5 downto 0); k3 : in std_logic_vector(5 downto 0); k4 : in std_logic_vector(5 downto 0); k5 : in std_logic_vector(5 downto 0); k6 : in std_logic_vector(5 downto 0); k7 : in std_logic_vector(5 downto 0); k8 : in std_logic_vector(5 downto 0); k9 : in std_logic_vector(5 downto 0); k10 : in std_logic_vector(5 downto 0); k11 : in std_logic_vector(5 downto 0); k12 : in std_logic_vector(5 downto 0); k13 : in std_logic_vector(5 downto 0); k14 : in std_logic_vector(5 downto 0); k15 : in std_logic_vector(5 downto 0); k16 : in std_logic_vector(5 downto 0); address : out std_logic_vector(3 downto 0); min : out std_logic_vector(5 downto 0)); end component;

component TOTALACSUNITS port( B0 : in std_logic_vector(3 downto 0); B1 : in std_logic_vector(3 downto 0); B2 : in std_logic_vector(3 downto 0); B3 : in std_logic_vector(3 downto 0); clk : in std_logic; T : in std_logic_vector(3 downto 0); reset : in std_logic; minimum : in std_logic_vector(5 downto 0); d16 : out std_logic_vector(15 downto 0); re_traceback,re_counter : out std_logic; com_smu,com_traceback : in std_logic; IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7,IN8, IN9,IN10,IN11,IN12,IN13,IN14,IN15 : out std_logic_vector(5 downto

0)); end component;

component tracebackunitnew port( clk1 : in std_logic; decisionbits : in std_logic_vector(15 downto 0); address : in std_logic_vector(3 downto 0); output : out std_logic; complete_smu : out std_logic; complete_traceback : out std_logic; reset_traceback : in std_logic; reset_counter : in std_logic); end component;

signal B0,B1,B2,B3 : std_logic_vector(3 downto 0); signal addre : std_logic_vector(3 downto 0); signal d116 : std_logic_vector(15 downto 0); signal minimm : std_logic_vector(5 downto 0); signal r_traceback,r_counter,co_smu,co_traceback : std_logic; signal YN0,YN1,YN2,YN3,YN4,YN5,YN6,YN7,YN8,YN9,YN10,YN11,YN12,YN13,YN14,YN15 : std_logic_vector(5 downto 0);

begin

BMU1 : BMUnew port map ( S1 => s1, S2 => s2, BM0 => B0, BM1 => B1, BM2 => B2, BM3 => B3);

TREE : comparatortreenew port map ( k1 => YN0, k2 => YN1, k3 => YN2, k4 => YN3, k5 => YN4, k6 => YN5, k7 => YN6, k8 => YN7, k9 => YN8, k10 => YN9, k11 => YN10, k12 => YN11, k13 => YN12, k14 => YN13, k15 => YN14, k16 => YN15, address => addre, min => minimm );

TRACEBACK : tracebackunitnew port map ( clk1 => clk1, decisionbits => d116, address => addre, output => val, complete_smu => co_smu, complete_traceback => co_traceback, reset_traceback => r_traceback, reset_counter => r_counter);

TACS : totalacsunits port map( B0 => B0, B1 => B1, B2 => B2, B3 => B3, clk => clk, T => T3, reset => reset, minimum => minimm, d16 => d116, re_traceback => r_traceback, re_counter => r_counter, com_smu => co_smu, com_traceback => co_traceback, IN0 => YN0, IN1 => YN1, IN2 => YN2, IN3 => YN3, IN4 => YN4, IN5 => YN5, IN6 => YN6, IN7 => YN7, IN8 => YN8, IN9 => YN9, IN10 =>YN10, IN11 => YN11, IN12 => YN12, IN13 => YN13, IN14 => YN14, IN15 => YN15); end Behavioral;

I am giving the error again.

FATAL_ERROR:HDLParsers:vhptype.c:270:$Id: vhptype.c,v 1.1 2001/03/22

18:59:29 kingsley Exp $:200 - INTERNAL ERROR... while p arsing G:/sunil/totaldecoder.vhd line 108. Contact your hot line. Process will terminate. To resolve this error, please con sult the Answers Database and other online resources at EXEWRAP detected a return code of '1' from program 'F:/Xilinx/bin/nt/xst.exe'

Done: failed with exit code: 0001.