Is the Xilinx Virtex 4 the fastest FPGA available in in-circuit reprogrammable format?
Their data sheet claims 450MHz PPC and 500MHz DSP. The -12 speed grade of the XC4VFX40 or 60 devcies sound like they won't be available until next year, though.
I couldn't find definitive data in the Altera literature about the speed of the Stratix II parts. Do these parts run at speeds approaching the Virtex 4 parts?
Does Lattice offer high-speed devices with built-in microprocessor, DSP, and RAM support? It appears the EC family supports RAM at up to 200MHz.
Lattice devices have built in DSP and RAM, but no microprocessor. Their current range of devices are more comparable to Spartan 3 in terms of performance and price, than to Virtex 4.
Our latest benchmarking shows that the fastest Stratix II speed grade (the -3 devices) outperform the fastest Virtex-4 speed grade (-12) by 18% on average, with SII outperforming V4 on over 80% of tested designs. See
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for details -- there is a link to a whitepaper describing our comparison methodology.
You can visit Xilinx's web page to see what they claim for the SII vs. V4 comparison -- as you can imagine the two companies do not see eye to eye :-)
One side note: For Altera devices, lower numbers are faster (I believe way back in time the number was related to some path delay in the chip). For Xilinx devices, higher numbers are faster. So a SII -3 is faster than a SII -5, and V4 -10 is slower than V4 -12.
As can be expected, any FPGA's performance will vary based on the coding style, the application, and the use of device specific features. We use more than 100 designs from custoemrs to compare performance just for that reason. We also evaluate each design carefully to make sure that it is using the device resources appropriately (both for us, and our competitors).
Xilinx claims the high road, both in superior performance, and superior density (size). We claim more than that, actually...
A quick browse of the websites will provide you with more information than you can read in one lifetime.
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is a good review of V4, which illustrate how we beat all other FPGAs in EVERY category.
In fact, some categories there is no competition at all (ie 10 Gb/s serial IOs, IBM PPC, and Ethernet MACs).
Quite a claim (at first glance), but consistent with Xilinx values, we wouldn't make such a claim if it wasn't true, and backed by data, evaluation boards, white papers, applications notes, and customer testimonials.
Superior in EVERY way, Virtex 4.
Aust> Is the Xilinx Virtex 4 the fastest FPGA available in in-circuit
Xilinx used to do the same tihng. But when they were in danger (with the continued processing/development) of having a XC4000 - -1, they decided to switch the numbering scheme to "Higher is faster" with the Virtex line.
--
Nicholas C. Weaver. to reply email to "nweaver" at the domain
icsi.berkeley.edu
NLP stands for Neuro-Linguistic Programming... (I had to google that...)
IT is interesting that despite this frenzy about top speed, most users always buy the (cheaper) slow speed grades... Makes you wonder what's so important.
This reminds me of car advertising in Europe, where top speed used to be the big issue. "My fast 260 kmph BMW is better than your slow 255 kmph Mercedes !" Nowadays, the distinction is more about important issues, like the number of cupholders and foldable back seats... Peter Alfke
"Peter Alfke" schrieb im Newsbeitrag news: snipped-for-privacy@g14g2000cwa.googlegroups.com...
"Geiz ist geil", a slogan heavily used in advertising of a big electronic market chain. ;-)
Even on the Autobahn here, most top ten cars are limited by electronic, not engine power. So all the BMW, Mercedes, Porsche easily reach 250 km/h, when the electronic suddenly decides, "That enough, dude".
Even though the Xilinx and Altera FPGA appear very similar there are subtle differences which leads to different choices depending on the target for you design. I'll give you a simple example, Block RAMs. The Block RAMs in Virtex2P are faster then the Block RAMs in the Stratix II in single pipeline mode, i.e. no output register. However the Stratix II includes an optional output register in the Block RAM component, the Virtex2P doesn't have an output register (the Virtex4 does). If you use the output register in the Stratix II then the Stratix II will be faster, if you don't then the Virtex2P will be faster. So if you were targeting a design for the Virtex2P you probably won't register the outputs of your Block RAMs unless you are shooting for a very high frequency because the registers use up precious flip flips. If you then move the design to a Virtex2P it will run slower. However if you were designing for the Stratix II you would use output register because they are free and they'll simplify routers task because it will have a easier time meeting timing. If you then move the design to a Virtex2P it will be bigger and it might be slower because the output register would have to be instantiated in flip flops. There are lots of choices like that, another example is LUT RAMs and LUT based shift registers which Xilinx has and Altera doesn't. because they are there you'll use them if you are targeting Xilinx which means that that design will be bigger and slower if you put it into an Altera part. This sort of thing goes both ways, the Altera M512 RAM is 32 deep so if you are targeting an Altera part you will probably make your small FIFOs 32 words deep, if you then move it to a Xilinx part you'll need 4 LUTs per bit which will make the design bigger and slower in the Xilinx part.
The bottom line is that if Altera and Xilinx each gather up a 1000 designs from their own customer bases and then build for both architectures each will find that their own architecture is 20% faster then the other guy's. Neither will be lying, the results will clearly show that their own architecture is significantly better in an overwhelming number of cases. The problem is in the sample, if you ask Germans and Englishmen which is better Lager or Ale you'll get a different answer.
Many thanks to all who responded. Very helpful input. It's given me some good data to examine.
My application requires multiple stamps of very fast DSPs (for data acquistion and filtering), a high-speed RAM interface (to store the acquistion results), failry high-speed disk operations (to off-load and archive the acquistion results), and several slower-speed housekeeping tasks (user control input and display output, etc.), which could be handled by an embedded "soft" processor.
It sounds like the Virtex 4 or the Stratix II is probably the right approach in this application.
We choose to show the products in their best mode, not their worst, so that may be a valid assumption.
It may also be that we used the tools that are shipped with the product, I just don't know.
Generally speaking, the synthesis tool may also be a factor in performance variations. Hopefully over the large number of test cases, the choice of tools becomes a minor effect, but sensitivity to tool usage is definitely something very real.
I have heard from customers that at various times, one tool or another has been "superior." Our policy is to share all performance improvements in our synthesis tool with our partners, as we are not in the business of selling synthesis tools, but rather using our own synthesis tool refine and evaluate our architectures.
Just as for any individual customer, one FPGA or the other may be "superior" in terms of performance, they are close enough in performance that only by evaluating a large number of designs can the trend be seen.
But my posting was not so much about the speed debate, but more about the overall product superiority: static power 1-5 watts less, SI for ground bounce up to 8X less, added features (SSIO, DSP48, E-MACs, PPC, MGT, FIFO-BRAM, FRAME_ECC, etc...).
*Sigh*, here we go again. Raw device speed isn't the whole answer, and neither is the list of device features. I could easily design a suite of test circuits that could 'definitively' show either the stratixII or the virtex4 as being the faster device, depending on which one I wanted to 'win'. All that really proves is what I've said for the past 12 years, which is if you really want to wring out the most performance from a device you MUST tailor your design to that device. Doing so will get you the maximum speed in/ that/ device, but at the same time will generally hurt the performance in the other devices that it wasn't tailored to.
When deciding on a device, chose based on your comfort level with the family and its tools, and how well the feature set of that chip augment your design. Both are good products, and you won't go wrong with either as long as you pay attention to the device architecture as you develop your design.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Especially when the final (newer) Stratix II timing models have DSPs & Memories running much faster than in older releases, eliminating some of X's favourite "up to" numbers quoted...
Ray -- please don't take a job working for any of the FPGA vendors! Your vendor-independent voice of reason is sorely needed here.
I'm sure I speak for many when I say that I'm bored of the A vs X pissing match. I don't care which FPGAs were the first ones built on a
90 nm process! I don't care that a part is going to be $2 each when purchased in quantities of a HALF MILLION in 2007. (Wish I did care, but that's a different story.) (Is the config PROM gonna be twenty cents?)
Users want:
a) tools that work b) parts we can buy in the quantities we need in the timeframe required by our schedules.
I think the best thing about the availability of free tools is that if we're not pushing the envelope (read: using the latest/greatest), we can keep all vendor tools installed on our development machines and choose the parts that make the most sense.
-a
----------------------- Andy Peters Tucson, AZ devel at latke dot net
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