fast universal compression scheme and its implementation in VHDL

Hi folks,

my name is Jens and I am student of the Technical University Berlin. Through my course of study in microelectronics VHDL design is becoming my favorite hobby. My other interests are signal processing and compression in general. Lately I purchased an FPGA Evalution board second-hand (guess where?) and I am now starting my first "private" implementations. Just to give you a short intro... ;-)

I am interested in implementing compression algorithms using VHDL on an FPGA. I want to build a data transmission system that compresses portions of the incoming data (not the whole data but "frames" of like 800 bytes) on-the-fly. In my search for a fast (i.e. real-time capable at a "desired" data rate of - let's say - 300 MHZ?) "universal" compression scheme I came across the following stepping stones:

- is there any free example code for compression algorithms available in VHDL to get an overview and a first impression of implementation complexity?

- what would you think are the most promising algorithms for my purpose (i.e. when statistics and semantics of the input data are unknown), first of all I thought of delta encoding, sorted RLE, LZ, ....?

- as the input data is unknown the álgorithm must be lossless, reducing redundancy (if possible), not irrelevancy. what are the theoretical limits of "universal" compression, not emphazizing one particular statistical property (like similar by values in succession)?

- what is meant by the keyword "systolic implementations" and "pipeling" in that particular context? I came across that very often lately

- what if my code gains different compression ratios for consecutive data portions? surely a FIFO can decouple input and output rate but eventually the FIFO will underflow?

Thanks for you help + support in advance, any comments, hints and help is appreciated!

Bye Jens

P.S.: I'm looking for the standard works "Sayood, Khalid: Introduction to data compression, Academic Press, 199x or 200x" and/or ". Salomon: Data Compression, Springer-Verlag, New York, 200x". Are there any sources of an electronic copy (ps, pfd, etc.) or transcriptions?

Reply to
Jens Mander
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"Jens Mander" schrieb im Newsbeitrag news:d8bbs2$mme$ snipped-for-privacy@mamenchi.zrz.TU-Berlin.DE...

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Hello Jens,

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First things first. Do you have a reasonable amount of expirience using VHDL and FPGAs? I mean, are you able to do more than just flashing a LED using a FPGA? Something in the range of building a UART, using FIFOs (maybe building a synchronous FIFO your own) etc. IF so, ok go ahead. IF NOT, I strongly suggest to get to this level first before continuing.

300 MHz isn't a data rate. (that why my comment above). So whats your desired data rate? 300 Mbit/s? 300 Mbytes/s?

complexity?

Do you had a look at software compession routines? Study them. Understand them. Convert them. Start with an easy one.

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Pipelinig is a technique to spread the data processing over multiple clock cycles. Doing so allows to increase the clocking speed, since the individual logic operations are simpler (and so faster). Penalty is increased latency. This should be enough to start a research, isnt it?

Bad luck. FIFO too small and compression routine too bad.

Regards Falk

Reply to
Falk Brunner

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