Hi, I'm building a S/PDIF Receiver for implementation on spartan 3 fpga. I don't have an expensive DSO to analyze the spdif signals : ( So i decided to build a sampler and run it fast enough, say 10-20 times the spdif signal frequency and the display the signal on some audio editing software.(remember i'm sampling only digital signals so there's no ADC involved)
So here's my setup, I'm taking the input signal and passing it through a 2 flop synchroniser, then i'm packing 8 samples to a byte and writing it to a 16K block ram fifo on fpga. The sampled data is sent to the PC through FTDI's UM245R module. At reset the sampler samples
16K X 8 samples , writes to fifo and stops. the system is running at 50Mhz (also sampling input signal at 50msps), the sampling packing and writing to fifo is done on the fly. Then the usb module writes the data to the usb port in its own time.The problem: When i sample signals from the same clock domain (i.e, a divided clock from 50Mhz sys clk) the are no problems. I see perfect clock signal with nearly 50% duty cycle and no glitches in sight. but once i feed an external signal signal such as the spdif or a clock from a different oscillator, the signal seems to closely match the frequency of the input but I see a lot of glitches. Most of the glitches are one sample wide and very close to the rising/falling edges of the input signal. but there are also quite a few glitches in stable 1's /0's regions of the input signal.
So what could be the possible cause of these glitches? I can understand glitches near the edges which could be due to metastability but in the middle of stable 1's and 0's there could be no issue of metastability. I have used 2 flop synchroniser like the ones used in asynchronous fifo's. What else can i do the eliminate the glitches?