Hello all, In my design there is a possibility (its dynamic) that a register may get connect to inputs of 172 gates. Is this possible on Virtex E or any other xilinx FPGA. And is it possible in the real silicon i am asking about industry standards. Or is there any other way i can achive this. By changing my design etc. Sumesh V S
I have a reset signal that is synchronised by 4 FF's with a fan-out of
2,700-odd. However this signal is used as an async reset so it's probably going to preset/clear rather than Din ports...I could imagine you could reduce the fan-out (if required) with a tree of FF's, if you can tolerate the added delay.
Regards, Mark
Sorry, I'm using an Altera part...
Regards, Mark
This is no problem at all. It might be a little slow. In that case you can duplicate your register to balance the fanout between two stages.
Kolja Sulimma
S V S,
There should be no problem with what you describe here.
The place and route tool will use LUTs for routing, if there is not enough interconnect. The place and route tool may multiply the FF, depending if there is another one, so that there are two "sampling" stages.
Vladislav
Ok ... But what about the dynamic property of the routing. Is the PAR tool wil cnsider all the possibilites that may arise only at working time. Kolja are you suggesting a manual duplication or the method suggested by the Muravin.
There aren't any issues with implementing what you want (a register with a fanout of 172 loads in a Virtex FPGA). Virtex FPGAs use a fully buffered interconnect which means that every time a routing resource connects to another routing resource it goes through a buffer that is appropriately sized for the wire that it drives.
In Virtex any single buffer/wire should see only 1-3 loads with the exception of a "long wire" that covers the length or width of the device that might see up to 20 loads depending on the device size. The timing analyzer will correctly report the timing of the net depending on the resources that are used.
Ed
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