false path

See:

This is quite a simple example but you can see that the data can only "flow" from xy1_s to xa2_s and from xa1_s to xy2_s. This means that the path through both multipliers is false. If the tpd of the multiplier is 100ns and the adder 10ns then your P&R tool might give you a total tpd of 200ns rather than 110ns.

Finding these path is normally very time consuming and the way to tackle it is to only focus on the most negative slag path and work your way through the schematic and RTL. There are also tools that find these path automatically (e.g. Focus from Fishtail) but they are more for ASIC's than for FPGA's although I know that Focus also supports FPGA's,

You might also want to google for Static and Dynamic sensitised paths,

Hans