Hi,
when using Xilinx par 7.1.03i and implementing some logic on a Xilinx XC31000, I get a warning regarding the routing of my main clock that I don't understand. Could someone give an explaination as well as a way to avoid it?
WARNING:Route - CLK Net:s_clk_120MHz may have excessive skew because 5858 CLK pins failed to route using a CLK template.
Many thanks, Eric.