Hello,
I recently release Confluence 0.7.3. The big addition is the ability to instantiate custom Verilog and VHDL modules from with in Confluence. This feature is especially useful for instantiating FPGA specific blocks with configurable constraints (timing, RLOC, etc.).
Both sequential and combinatorial modules are supported, and modules may include any number of configuration parameters. You can also create C and Python models for your external components to integrate with Confluence generated C and Python for simulation.
Installation is easier too. Just extract the tarball (_.tar.gz), set an environment variable, update the path, and your done.
I also removed license protection. Like most tool users, I hate dealing with LM. So Confluence is now on the honor system. My licensing policy still stands: free for personal and academic use, and 1 free seat per company for commercial endeavors. Companies can also install any number of copies for evaluation.
Download at:
Confluence runs on Linux (x86), Cygwin (windows), and Solaris.
Regards, Tom
-- Tom Hawkins Launchbird Design Systems, Inc.
952-200-3790