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external clock frequency doubles

Hi People,

I am attempting to interface the Xilinx Virtex - II Pro FPGA with a quad channel codec.

I am using XC2VP30-FF896 FPGA on the Xilinx University Program Development Board.I had applied a 2.048MHz TDM clock to the FPGA pin B16, which is the GCLK6S ( Global Clock Input).

My problem is that by the time this clock reaches my IP on the OPB Bus , its frequency doubles!! I have confirmed this by checking pulses generated on the basis of this clock, on a Digital Oscilloscope.

I have confirmed that I have not instantiated a DCM in the external clock path . The resource utilisation shows that the system uses only

1 DCM , which is attached to the sys_clk_s.

For now , to make my system work , i have divided the clock frequency inside my IP and then applied it to the individual block. But the confusion of why this exactly happened still remains.

Thanks Venu

Reply to
Venu
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Venu, I am sure that your problem is caused by poor signal integrity at the clock input to the FPGA. There may be overshoot, undershoot and ringing, which causes the FPGA to interpret the falling clock edge as another rising clock edge. Try to clean up the clock signal, terminate it properly.

2 MHz is a very low clock frequency, and it might have a slow rise/ fall time, which might be another source of double-triggering caused by noise during the transition. Peter Alfke, from home.

Reply to
Peter Alfke

Thanks for the input Peter. I have started looking into the pointers that you have provided.

Just to make this discussion complete, I would like to record one further observation that I made.

The 2 MHz clock is driving the FPGA ( as I had previously mentioned ) as well as a codec on the board. When the codec power supply is switched off , then the FPGA is generating pulses at pulses at 500 ns width ( 1 clock period of the 2MHz clock) . But as soon as the codec is turned on , the FPGA pulses are now of 250 ns width. In both the cases though , the external clock frequency remains 2.048 MHz.

Uptil now my ucf setting for the clock pin input was as follows NET TDM_CLK_pin LOC = "B16"; NET TDM_CLK_pin IOSTANDARD = LVCMOS25;

I will try to use any of the IOB settings to terminate the clock properly. If I can solve this problem, I will report it in this discussion.

Thanks once again Venu

Peter Alfke wrote:

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Venu

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Peter Alfke

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