1. Home
  2. Field-Programmable Gate Arrays
  3. extending a signal pulse

extending a signal pulse

You could use a SRL16/DFF (with clock-enable and synchronous clear) combination for this. The input pulse - which is high for one clock cycle -sets the FF output, and a delayed version of this pulse clears it after a number of clock cycles. The depth of the SLR16 sets the length of the output pulse. Note that the output pulse is delayed by one clock cycle with respect to the input pulse.

_______ | | +--| SRL16 |------+ | |_______| | | | | ______ | | | | | short pulse -----+--|CE Q|----------- long pulse | | | 1--|D | | | | | CLK--|> | | | | | ---|CLR | | | |______| | | | +-----------------+

Regards, Guy.

Reply to
Guy Eschemann
Loading thread data ...

Yes, that looks like a good solution. I'll give that a try later.

For more ascii art, see:

formatting link
You could use a SRL16/DFF (with clock-enable and synchronous clear)

--=20

----------------------------------------------- Please remove the x's in the email address if replying to me personally.

Johan Bernsp=E5ng, snipped-for-privacy@xfoix.se

Reply to
Johan Bernspång

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.