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Execute from SPI flash

Execute from SPI flash has always appealed as one way to reduce the PCB cost of the Code memory needed by Soft CPUs. Winbond have had Double rate SPI devices at 150MBd, and I see they plan to release Quad-SPI devices, that target Execute of code direct from the Flash.

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News : ["To address this need, Winbond will introduce a new class of high-performance serial flash memories later this year. The new family features Quad-SPI with six times the transfer rate of standard serial flash and greater performance than most parallel flash memories. This new line is targeted at applications that execute code directly from the SPI bus to significantly reduce system costs. Winbond will initiate this Quad-SPI family with a 16-megabit flash memory."]

Natural next step, is to tweak Soft-CPUs to take advantage of this type of memory.

-jg

Reply to
Jim Granville
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More info: Advance data is here

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Still an 8 pin package (or SO16 where die is too large )

Best speed is from Fast Read Quad I/O opcode

Looks like the first byte is 1-bit SPI (8Ck), then the 32 bit address is loaded 4 bits wide (8Ck), then 4 wait clocks, and then bytes stream out two Ck per byte, so the latency to first byte is 8+8+4+2 = 20-22clks, and the Speed-Equivalent-Skip is 10 bytes - ie for short forward jumps, of up to 10 bytes, you are better to simply skip, than re-address. Clock is 80MHz, gives 320MBd, or 40 MBytes/s memory bandwith. Enough for some serious uC programming, and you can split into 2 SPI devices, and double that again, or perhaps x3, for 18-24 bit opcode cores ?

-jg

Reply to
Jim Granville

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At what point do you call it a parallel flash (admittedly with an address counter built in :-)

Cheers, Martin

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Reply to
Martin Thompson

You are right :) - they are inching [nibbling ? ;) ] their way back to the memory segment that has mostly died off (except in some game cartridges ?) of Address latched and Clocked Code Flash/Rom Memory.

Still, getting a Nibble-wide memory in a 8 pin package is quite nice, and using 2-3-4 of these is probably quite practical.

From an energy and EMC angle, it makes much more sense to have a loadable address counter, so I hope these contine to expand. Next, we might see Byte-wide ones in SO16 ?

-jg

Reply to
Jim Granville

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