ethernet core on a xc3s200

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Hi everyone,

I'm stuck implementing a hardware design on a Spartan3 Starter Board
which uses a xc3s200 fpga.
After several times trying to include an opb_ethernet core on to the
design I never acheive to generate the bitstream.
I get the following messages whilst mapping:

Design Summary:
Number of errors:      1
Number of warnings:   83
Logic Utilization:
   Total Number Slice Registers:     3,035 out of   3,840   79%
     Number used as Flip Flops:                 3,034
     Number used as Latches:                        1
   Number of 4 input LUTs:           3,739 out of   3,840   97%
Logic Distribution:
   Number of occupied Slices:                        2,625 out of
1,920  136%
     Number of Slices containing only related logic:   2,180 out of
2,625   83%
     Number of Slices containing unrelated logic:        445 out of
2,625   16%
       *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          4,466 out of   3,840  116% (OVERMAPPED)
   Number used as logic:              3,739
   Number used as a route-thru:         154
   Number used for Dual Port RAMs:      280
     (Two LUTs used per Dual Port RAM)
   Number used as Shift registers:      293
   Number of bonded IOBs:               62 out of     173   35%
     IOB Flip Flops:                    58
   Number of Block RAMs:               12 out of      12  100%
   Number of MULT18X18s:                3 out of      12   25%
   Number of GCLKs:                     2 out of       8   25%
   Number of BSCANs:                    1 out of       1  100%

    Number of RPM macros:            5
Total equivalent gate count for design:  887,513
Additional JTAG gate count for IOBs:  2,976
Peak Memory Usage:  113 MB

Does this mean I cannot use an ethernet core in my design??
Is there any way of reducing the logic used by the ethernet core??
Could anybody please help me out?

I have tried using ethernet lite core but it's no use to me since I have
to be using lwIP library which isn't supported with ethernet lite.


Re: ethernet core on a xc3s200
Looks like no chance dude. better go for higher device.

Re: ethernet core on a xc3s200

Hi Adrian

Quoted text here. Click to load it

This part of your design report shows that the core does not fit into
the X3S200 device.
With some luck you can use different synthesis constraints and higher
efforts for the mapping and PAR to reduce the number of occupied Slices.

Have a nice synthesis

Re: ethernet core on a xc3s200
backhus escribió:
Quoted text here. Click to load it

Hi Eilert,

Tnankyou for your reply.
How can I configure EDK for using other/better synthesis constraints and
higher efforts?


Re: ethernet core on a xc3s200

Quoted text here. Click to load it

Howdy Adrian,

You may be able to drive the LUT utilization and the number of occupied
slices down closer to 100% by turning on timing-based mapping (timing)
and turning your -k (Map to input functions) option on MAP to its
maximum, but I'd be a little surprised if made your design small enough
to fit.  Are you sure there isn't logic you can optimize manually

Good luck,20%


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