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ERROR:Xst:827 - bad synchronous description

Hi,

I have a problem synthesizing a VHDL code. The error is the following: ERROR:Xst:827 - "C:/Xilinx/work/MYPROJECT/projectfile.vhd" line 134: Signal codeLen cannot be synthesized, bad synchronous description. The answer record # 14047: XST - "ERROR:Xst:827 suggests using clock events in the topmost IF statement, which I am doing (The synchronous element description is based on the 'event VHDL attribute. In order for XST to infer a synchronous element, the 'event VHDL attribute must be present in the topmost "IF" statement of your process. Furthermore, there should be no embedded 'event statements within a process.)

Here is the suggested example: synchronous_description : process (clk, reset) is begin if reset = '1' then -- asynchronous reset q

Reply to
bobrics
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Remove the state from the dependency list and the elsif expression. You don't need the state dependency. Move the state = 0 expression to the statement which elsif evaluates.

HTH.

Reply to
mk

Thank you! That actually makes sense - there's no need to keep multiple clock signals and then your sensitivity list shrinks down to two signals: process(reset, clk)

mk wrote:

Reply to
bobrics

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