Error Using Block Ram in model sim XE 5.7

I'm using ISE 6.2i and when ever i use a Block RAM I cant see the Ram output Data the error is Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at simulation time 0.150 ns with respect to CLKB port at simulation time

0.150 ns. Expected setup time is 0.100 ns # Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at simulation time 0.250 ns with respect to CLKB port at simulation time 0.250 ns. Expected setup time is 0.100 ns # Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at simulation time 0.350 ns with respect to CLKB port at simulation time 0.350 ns. Expected setup time is 0.100 ns # Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at simulation time 0.450 ns with respect to CLKB port at simulation time 0.450 ns. Expected setup time is 0.100 ns

the Enable pin is high and I change the Address but the out put is always

0 can any one help me with this ?? thanks THE UNFORGIVEN

It looks to me like you might be using an older version of the Xilinx library. That message has been changed to something like:

Memory Collision Error on RAMB4_S16_S16:NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst at simulation time

0.450 ns. A read was performed on address 0000 (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.

I suggest you update the XE version and/or get the latest version of the libraries and rerun the simulation to see if you get an error message like the one above and if it makes more sense as to what the problem is with the design. Memory collisions are a design issue that must be accounted for proper circuit operation and that is what this error is trying to indicate. Also, looking at the times reported in the error messages, it looks like you might have a fairly fast clock in your testbench, 100 ps or 10 GHz which is far faster than the FPGA could possibly support and likely a mistake that should be corrected. I also suggest you hold off putting simulation stimulus for your design until after 100 ns has passed so that for timing simulation, you are not attempting to simulate during the global set/reset phase of the device simulation.

-- Brian

unforgiven wrote: