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ERROR: NgdBuild:604 - logical block

Hi all:

I am trying to add customized IP to microblaze using FSL channel. The customized IP includes block ram generated by coregen tool and wrapper vhdl file to use this block-ram. Under pcores directory, the files are arranged as follows:

pcores/dual_ram_v 1_00_a/ data/dual_ram_v2_1_0.bdd dual_ram_v2_1_0.pao dual_ram_v2_1_0.mpd pcores/dual_ram_v 1_00_a/ hdl/vhdl/input_ram_wrapper.vhd (wrapper vhd file) pcores/dual_ram_v 1_00_a/ netlist/input_ram.edn (file created by coregen).

BDD file contains the following:

FILES input_ram.edn.

When I tried to generate bitstream, I receive the following message:

ERROR: NgdBuild:604 - logical block 'dual_ram_0/dual_ram_0/inst_input_ram/ram_name' with type 'input_ram' could not be solved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'input_ram' is not supported in target 'virtex2p'.

How can I overcome the above error? I think that I made mistake in

*.bbd file and netlist directory. If I added wrong file in the netlist directory, please let me know the correct file that I needed to add there and let me know how I can create those relevant file. Please help me to overcome this problem.

Thanks

Reply to
Mayil
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Have you set the STYLE in the mpd file to "MIX" so EDK knows to use the bbd and associated netlists?

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Paul

Mayil wrote:

Reply to
Paul Hartke

Hi Paul:

As you pointed out, I forgot to include style option as "MIX" in the mpd file. After updating the .mpd file, it works fine.

Thanks for your help, Aroul

Reply to
Mayil

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