ERROR:NgdBuild:604

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Hi People ,

I am using a custom BRAM , but it is not getting synthesised , it keeps
giving the error that
   ERROR:NgdBuild:604 - logical block
'my_transmitter_0/my_transmitter_0/dpram0'
   with type 'custom_bram_0' could not be resolved. A pin name
misspelling can
   cause this, a missing edif or ngc file, or the misspelling of a type
name.
   Symbol 'custom_bram_0' is not supported in target 'virtex2p'.

custom BRAM generated using ----> Xilinx Core Generator
Xilinx ISE functional simulation  -----> completed successfully
Xilinx EDK BFM simulation      -----> completed successfully
Netlist                                   ------> completed successully
Bit Stream Generation           --------> FAILURE

There has been traffic on this groups regarding the problem that I am
facing, but none of the solutions that have been proposed are working
in my case.

I have designed a OPB Master Slave Peripheral , in which I have used a
Dual Port RAM generated by XilinxCoreGenerator. I name this core
custom_bram.The following files are generated
1)custom_bram.asy     2)custom_bram.edn  3)custom_bram.sym
4)custom_bram.v
5)custom_bram.veo      6)custom_bram.vhd  7)custom_bram.vho
8)custom_bram.xco
9)custom_bram_flist.txt

I copied custom_bram.vhd into my user directory and instantiated it as
a component in the main module.

Things that I have tried:
1) custom_bram uses an entity called XilinxCoreLib.blkmemdp_v6_3
defined in the library XilinxCoreLib . I copied all the related files
from the blkmemdp_v6_3 into the pcores/hdl/vhdl directory.

2) i copied the custom_bram.edn file generated into a directory called
/pcores/netlist and in the my_transmitter_0.mpd file made an entry
specifying that
OPTIONS STYLE = MIX.

3) In the instantiation of the custom_bram i have tried
my_transmitter_v1_00_0.custom_bram ( as suggested in one of the posts
on this group)

4) I am using 4 block rams in this designs ... In of the documents that
I read , it was stated that you cannot make multiple instantiations of
the same module, so i made 4 copies of the custom_bram , renamed them
and referred to each only once

None of these have worked .... Any ideas ? :)


Thanks
Venu


Re: ERROR:NgdBuild:604
Venu,

you must include custom_bram.bbd (dir custom_bram/data) file to specify
all netlists:

Files
################################################################################
custom_bram.edn, XilinxCoreLib.blkmemdp_v6_3.edn


Use "," to separate multiple files specs.

Then copy netlist files to "dir custom_bram/netlist" dir.
That should do.

Cheers,

Guru


Venu wrote:
Quoted text here. Click to load it


Re: ERROR:NgdBuild:604
Thanks Guru,

I too was able to resolve the problem that I was facing ... I did as
follows:

1)I copied the file custom_bram.edn into the pcores/<core>/netlist
directory.
2)In the import peripheral wizard, I ticked the option to use netlist
files also as source files for the peripheral , and entered the path of
the netlist file specified above.

Now I am not getting any errors on bitstream generation.... :)

My solutions seems to be similar to yours except for one difference
..... in the directory created by Xilinx Core Lib , I DO NOT see any
file custom_bram.bbd ...

The *.bbd has been discussed in another posts also , but I am yet to
come across it in any of my designs... I am using EDK8.02.02i and
ISE8.02.03i.

"bbd" stands for black box description ... when does this concept come
into the design flow?

Thanks Again
Venu


Re: ERROR:NgdBuild:604
Maybe the wizard did it for you.
I was talking about the manual peripheral creation (i.e. without
wizard).

Cheers,

Guru


Venu wrote:
Quoted text here. Click to load it


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