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Error in simple code, plz help

Hello, I'm beginner in VHDL and practice with Xilinx ISE 9.2. I want to test and with generic, the code is similiar to "Circuit Design with VHDL" books cod and I don't understand where is problem. The synthesiser shows error: "Lin

  1. parse error, unexpected RANGE"

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gener_test is generic(n: integer := 8); port (input: in std_logic_vector(n-1 downto 0); output: out std_logic); end gener_test;

architecture Behavioral of gener_test is signal tmp1: std_logic_vector(n-2 downto 0);

--signal tmp2: std_logic; begin process(input) begin tmp1(0)

Reply to
VladimirM
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Remove the keyword "range" inside the for loop and also the braces. Your line 19 shd be "for i in 1 to n-2 loop"

-- parag

Reply to
beeraka

Hi Vladimir, for questions like this one comp.lang.vhdl is the prefered forum.

Your Code is just too complicated. I assume you want to practice with generics and loops.

1.) beeraka already mentiond that your loop is wrong (just for completeness) for i in 1 to n-2 loop

2.) You are assigning values to a signal tmp1 in a process. These values are not readable in while the process runs the first time. The Signal drivers are only updated at the end of a process. To force the process to run a second time (and more if needed) you need to include tmp1 in the sensitivity list of the process.

This would increase simulation time!

Maybe you should consider using variables instead. You also just need a simple std_logic this way:

e.g.: process(input) variable tmp1 : std_logic; begin tmp1 := '1'; -- initialize with default -- erased by the first '0' found for i in 0 to n-1 loop tmp1 := input(i) and tmp; end loop; output Hello,

Reply to
backhus

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